diff options
| author | Mihai Caraman <mihai.caraman@freescale.com> | 2014-04-17 09:26:14 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-04-30 01:24:50 (GMT) |
| commit | 993d07a27f10ad4a5d4847d964a6634674c4e2ee (patch) | |
| tree | c0824d859cbfd004cda14fb517cfe0e2068ea2cd /arch | |
| parent | b3737b95683d33e9c5bf71f9aa4bedf2a34527c3 (diff) | |
| download | linux-fsl-qoriq-993d07a27f10ad4a5d4847d964a6634674c4e2ee.tar.xz | |
powerpc/booke64: Add LRAT next and max entries to tlb_per_core structure
LRAT (Logical to Real Address Translation) is shared between hw threads.
Add LRAT next and max entries to tlb_per_core data structure and initialize them.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
(cherry picked and merged from sdk1.5 commit aa10cefcc1588338b3a80e842bc4db351dcec176)
Change-Id: If229acd9f4ae28fb49ce42132831d720bd436b84
Reviewed-on: http://git.am.freescale.net:8181/11558
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/include/asm/mmu-book3e.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/paca.h | 1 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 1 | ||||
| -rw-r--r-- | arch/powerpc/mm/fsl_booke_mmu.c | 9 |
4 files changed, 17 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h index ff53ea6..95c5865 100644 --- a/arch/powerpc/include/asm/mmu-book3e.h +++ b/arch/powerpc/include/asm/mmu-book3e.h @@ -219,6 +219,12 @@ #define TLBILX_T_CLASS2 6 #define TLBILX_T_CLASS3 7 +/* LRATCFG bits */ +#define LRATCFG_ASSOC 0xFF000000 +#define LRATCFG_LASIZE 0x00FE0000 +#define LRATCFG_LPID 0x00002000 +#define LRATCFG_NENTRY 0x00000FFF + #ifndef __ASSEMBLY__ #include <asm/bug.h> diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h index f873dd7..ba0483a 100644 --- a/arch/powerpc/include/asm/paca.h +++ b/arch/powerpc/include/asm/paca.h @@ -118,6 +118,7 @@ struct paca_struct { struct tlb_per_core { /* For software way selection, as on Freescale TLB1 */ u8 esel_next, esel_max, esel_first; + u8 lrat_next, lrat_max; /* Per-core spinlock for e6500 TLB handlers (no tlbsrx.) */ u8 lock; diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 56d1f27..0e37079 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -73,6 +73,7 @@ #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ #define SPRN_LPID 0x152 /* Logical Partition ID */ #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ +#define SPRN_LRATCFG 0x156 /* LRAT Configuration Register */ #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ #define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */ diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c index aada5a3..136871d 100644 --- a/arch/powerpc/mm/fsl_booke_mmu.c +++ b/arch/powerpc/mm/fsl_booke_mmu.c @@ -198,6 +198,15 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx) get_paca()->tlb_per_core.esel_max = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY; get_paca()->tlb_per_core.esel_first = i; + + get_paca()->tlb_per_core.lrat_next = 0; + if (((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V2) && + (mfspr(SPRN_MMUCFG) & MMUCFG_LRAT)) { + get_paca()->tlb_per_core.lrat_max = + mfspr(SPRN_LRATCFG) & LRATCFG_NENTRY; + } else { + get_paca()->tlb_per_core.lrat_max = 0; + } #endif return amount_mapped; |