Merge tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx into next/soc

From Michal Simek:
arm: Xilinx Zynq clock changes for v3.11

Change Xilinx Zynq DT clock description which reflects logical abstraction
of Zynq's clock tree.

- Refactor PLL driver
- Use new clock controller driver
- Change timer and uart drivers

* tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx:
  clk: zynq: Remove deprecated clock code
  arm: zynq: Migrate platform to clock controller
  clk: zynq: Add clock controller driver
  clk: zynq: Factor out PLL driver

Signed-off-by: Olof Johansson <olof@lixom.net>

3 files changed, 22 insertions, 55 deletions

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 14fb2e6..0dbee2c 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -49,16 +49,18 @@
 
 		uart0: uart@e0000000 {
 			compatible = "xlnx,xuartps";
+			clocks = <&clkc 23>, <&clkc 40>;
+			clock-names = "ref_clk", "aper_clk";
 			reg = <0xE0000000 0x1000>;
 			interrupts = <0 27 4>;
-			clocks = <&uart_clk 0>;
 		};
 
 		uart1: uart@e0001000 {
 			compatible = "xlnx,xuartps";
+			clocks = <&clkc 24>, <&clkc 41>;
+			clock-names = "ref_clk", "aper_clk";
 			reg = <0xE0001000 0x1000>;
 			interrupts = <0 50 4>;
-			clocks = <&uart_clk 1>;
 		};
 
 		slcr: slcr@f8000000 {
@@ -69,50 +71,21 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				ps_clk: ps_clk {
-					#clock-cells = <0>;
-					compatible = "fixed-clock";
-					/* clock-frequency set in board-specific file */
-					clock-output-names = "ps_clk";
-				};
-				armpll: armpll {
-					#clock-cells = <0>;
-					compatible = "xlnx,zynq-pll";
-					clocks = <&ps_clk>;
-					reg = <0x100 0x110>;
-					clock-output-names = "armpll";
-				};
-				ddrpll: ddrpll {
-					#clock-cells = <0>;
-					compatible = "xlnx,zynq-pll";
-					clocks = <&ps_clk>;
-					reg = <0x104 0x114>;
-					clock-output-names = "ddrpll";
-				};
-				iopll: iopll {
-					#clock-cells = <0>;
-					compatible = "xlnx,zynq-pll";
-					clocks = <&ps_clk>;
-					reg = <0x108 0x118>;
-					clock-output-names = "iopll";
-				};
-				uart_clk: uart_clk {
-					#clock-cells = <1>;
-					compatible = "xlnx,zynq-periph-clock";
-					clocks = <&iopll &armpll &ddrpll>;
-					reg = <0x154>;
-					clock-output-names = "uart0_ref_clk",
-							     "uart1_ref_clk";
-				};
-				cpu_clk: cpu_clk {
+				clkc: clkc {
 					#clock-cells = <1>;
-					compatible = "xlnx,zynq-cpu-clock";
-					clocks = <&iopll &armpll &ddrpll>;
-					reg = <0x120 0x1C4>;
-					clock-output-names = "cpu_6x4x",
-							     "cpu_3x2x",
-							     "cpu_2x",
-							     "cpu_1x";
+					compatible = "xlnx,ps7-clkc";
+					ps-clk-frequency = <33333333>;
+					clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+							"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+							"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+							"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+							"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+							"dma", "usb0_aper", "usb1_aper", "gem0_aper",
+							"gem1_aper", "sdio0_aper", "sdio1_aper",
+							"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+							"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+							"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+							"dbg_trc", "dbg_apb";
 				};
 			};
 		};
@@ -121,9 +94,8 @@
 			interrupt-parent = <&intc>;
 			interrupts = < 0 10 4 0 11 4 0 12 4 >;
 			compatible = "cdns,ttc";
+			clocks = <&clkc 6>;
 			reg = <0xF8001000 0x1000>;
-			clocks = <&cpu_clk 3>;
-			clock-names = "cpu_1x";
 			clock-ranges;
 		};
 
@@ -131,9 +103,8 @@
 			interrupt-parent = <&intc>;
 			interrupts = < 0 37 4 0 38 4 0 39 4 >;
 			compatible = "cdns,ttc";
+			clocks = <&clkc 6>;
 			reg = <0xF8002000 0x1000>;
-			clocks = <&cpu_clk 3>;
-			clock-names = "cpu_1x";
 			clock-ranges;
 		};
 		scutimer: scutimer@f8f00600 {
@@ -141,7 +112,7 @@
 			interrupts = < 1 13 0x301 >;
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = < 0xf8f00600 0x20 >;
-			clocks = <&cpu_clk 1>;
+			clocks = <&clkc 4>;
 		} ;
 	};
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 86f44d5..e25a307 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -28,7 +28,3 @@
 	};
 
 };
-
-&ps_clk {
-	clock-frequency = <33333330>;
-};
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index c70969b..50d008d 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -117,7 +117,7 @@ int __init zynq_slcr_init(void)
 
 	pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 
-	xilinx_zynq_clocks_init(zynq_slcr_base);
+	zynq_clock_init(zynq_slcr_base);
 
 	of_node_put(np);