esdhc: Workaround for eSDHC clock glitch issue

A-003980: SDHC: Glitch is generated on the card clock with software reset or
clock divider change
Description: A glitch may occur on the SDHC card clock when the software sets
the RSTA bit (software reset) in the system control register. It can also be
generated by setting the clock divider value. The glitch produced can cause
the external card to switch to an unknown state. The occurrence is not
deterministic.
Workaround:
A simple workaround is to disable the SD card clock before the software reset,
and enable it when the module resumes normal operation.
The Host and the SD card are in a master-slave relationship. The Host provides
clock and control transfer across the interface. Therefore, any existing
operation is discarded when the Host controller is reset.
The recommended flow is as follows:
1. Software disable bit[3], SDCLKEN, of the System Control Register
2. Trigger software reset and/or set clock divider
3. Check bit[3], SDSTB, of the Present State Register for stable clock
4. Enable bit[3], SDCLKEN, of the System Control Register
Using the above method, the eSDHC cannot send command or transfer data when
there is a glitch in the clock line, and the glitch does not cause any issue.

Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Change-Id: I43a6ef8fdffeeeb13bfef215825d417778ce0bf3
Reviewed-on: http://git.am.freescale.net:8181/5916
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>

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