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author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2013-04-03 14:40:39 (GMT) |
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committer | Stephen Warren <swarren@nvidia.com> | 2013-04-04 22:10:45 (GMT) |
commit | 0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f (patch) | |
tree | 989c920b532d4d5d7372c275ed828356cff9c581 /drivers/clk/tegra/clk.h | |
parent | 7ba28813b41120dd67329fd04dc732ea7fef05a0 (diff) | |
download | linux-fsl-qoriq-0b6525acd13f2d33cd3be86d0dbd2ddd1ffeda8f.tar.xz |
clk: tegra: Add PLL post divider table
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
-rw-r--r-- | drivers/clk/tegra/clk.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 17ddb22..925da45 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -117,6 +117,17 @@ struct tegra_clk_pll_freq_table { }; /** + * struct pdiv_map - map post divider to hw value + * + * @pdiv: post divider + * @hw_val: value to be written to the PLL hw + */ +struct pdiv_map { + u8 pdiv; + u8 hw_val; +}; + +/** * struct clk_pll_params - PLL parameters * * @input_min: Minimum input frequency @@ -146,6 +157,8 @@ struct tegra_clk_pll_params { u32 lock_bit_idx; u32 lock_enable_bit_idx; int lock_delay; + int max_p; + struct pdiv_map *pdiv_tohw; }; /** |