diff options
| author | Joseph Lo <josephl@nvidia.com> | 2013-08-12 09:40:01 (GMT) |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-08-12 18:22:39 (GMT) |
| commit | 444f9a8030ecda8dedd374fc3efed03d9f20e9cb (patch) | |
| tree | 396cc998a2265b70ef00d80c2b88f4f62132fe56 /drivers/clk/tegra | |
| parent | 5b795d051c61862cebf4f1d55edab6e9b3383b44 (diff) | |
| download | linux-fsl-qoriq-444f9a8030ecda8dedd374fc3efed03d9f20e9cb.tar.xz | |
ARM: tegra: config the polarity of the request of sys clock
When suspending to LP1 mode, the SYSCLK will be clock gated. And different
board may have different polarity of the request of SYSCLK, this patch
configure the polarity from the DT for the board.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra')
0 files changed, 0 insertions, 0 deletions