diff options
| author | Ulf Hansson <ulf.hansson@linaro.org> | 2012-10-10 11:42:28 (GMT) |
|---|---|---|
| committer | Mike Turquette <mturquette@ti.com> | 2012-11-10 00:47:07 (GMT) |
| commit | d6e99fa4f45a5f3c3029979680cf69c5a0579e6b (patch) | |
| tree | e458ba6c9946c868d2e7d94c08dfed2917504f2e /drivers/clk/ux500 | |
| parent | a816d250e866b01bd18b0dd2bcbe5f1951310094 (diff) | |
| download | linux-fsl-qoriq-d6e99fa4f45a5f3c3029979680cf69c5a0579e6b.tar.xz | |
clk: ux500: Add armss clk and fixup smp_twd clk for u8500
The new armss clk is a prcmu_scalable_rate clk which represents
the ARMSS clk. This then makes it possible to convert the smp_twd
clk to a fixed factor clock type, using a fixed divider of 2 and
with the armss clk as parent.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/ux500')
| -rw-r--r-- | drivers/clk/ux500/u8500_clk.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index 7bebf1f..955110d 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -206,16 +206,18 @@ void u8500_clk_init(void) clk_register_clkdev(clk, "dsilp2", "dsilink.2"); clk_register_clkdev(clk, "dsilp2", "mcde"); - clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS, - CLK_IS_ROOT|CLK_GET_RATE_NOCACHE| - CLK_IGNORE_UNUSED); + clk = clk_reg_prcmu_scalable_rate("armss", NULL, + PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, "armss", NULL); + + clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", + CLK_IGNORE_UNUSED, 1, 2); clk_register_clkdev(clk, NULL, "smp_twd"); /* * FIXME: Add special handled PRCMU clocks here: - * 1. clk_arm, use PRCMU_ARMCLK. - * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. - * 3. ab9540_clkout1yuv, see clkout0yuv + * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. + * 2. ab9540_clkout1yuv, see clkout0yuv */ /* PRCC P-clocks */ |