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| author | Tang Yuantian <Yuantian.Tang@freescale.com> | 2014-10-31 03:46:12 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:40:03 (GMT) |
| commit | 20476d6b030bd28813f261392a47d6eae649a0af (patch) | |
| tree | 4efa5c3858991a4b74896a4338ba5db4c59343ee /drivers/clk | |
| parent | 584eca5660d1849ed567c5036ac9da620dc2f755 (diff) | |
| download | linux-fsl-qoriq-20476d6b030bd28813f261392a47d6eae649a0af.tar.xz | |
clk: qoriq: correct variable num_parents calculation error
This variable should represent the clock number per PLL.
So, rename it and re-calculate it.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I2817f76a076d468073a870edc47e41ef43ffa07f
Reviewed-on: http://git.am.freescale.net:8181/22795
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk-qoriq.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index c674bbf..1fed044 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -20,7 +20,7 @@ struct cmux_clk { struct clk_hw hw; void __iomem *reg; u32 flags; - unsigned int num_parents; + unsigned int clk_per_pll; }; #define PLL_KILL BIT(31) @@ -35,7 +35,7 @@ static int cmux_set_parent(struct clk_hw *hw, u8 idx) struct cmux_clk *clk = to_cmux_clk(hw); u32 clksel; - clksel = ((idx / clk->num_parents) << 2) + idx % clk->num_parents; + clksel = ((idx / clk->clk_per_pll) << 2) + idx % clk->clk_per_pll; if (clk->flags & CLKSEL_ADJUST) clksel += 8; clksel = (clksel & 0xf) << CLKSEL_SHIFT; @@ -53,7 +53,7 @@ static u8 cmux_get_parent(struct clk_hw *hw) clksel = (clksel >> CLKSEL_SHIFT) & 0xf; if (clk->flags & CLKSEL_ADJUST) clksel -= 8; - clksel = (clksel >> 2) * clk->num_parents + clksel % 4; + clksel = (clksel >> 2) * clk->clk_per_pll + clksel % 4; return clksel; } @@ -73,6 +73,7 @@ static void __init core_mux_init(struct device_node *np) u32 offset; const char *clk_name; const char **parent_names; + struct of_phandle_args clkspec; rc = of_property_read_u32(np, "reg", &offset); if (rc) { @@ -101,7 +102,16 @@ static void __init core_mux_init(struct device_node *np) goto err_name; } cmux_clk->reg = base + offset; - cmux_clk->num_parents = count; + rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0, + &clkspec); + if (rc) { + pr_err("%s: parse clock node error\n", __func__); + goto err_clk; + } + + cmux_clk->clk_per_pll = of_property_count_strings(clkspec.np, + "clock-output-names"); + of_node_put(clkspec.np); node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"); if (node && (offset >= 0x80)) |