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| author | Tang Yuantian <Yuantian.Tang@freescale.com> | 2014-10-22 07:16:35 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:38:42 (GMT) |
| commit | d1562a24d43a095746da240ead98faf1d0ece899 (patch) | |
| tree | afd9f5d068eee8a22a55a163159a7fb766d78eb8 /drivers/clk | |
| parent | 0b6ce14d7f7739c0a3e53bdaaa7268da4d8b3519 (diff) | |
| download | linux-fsl-qoriq-d1562a24d43a095746da240ead98faf1d0ece899.tar.xz | |
clock: redefine variable clocks_per_pll as a struct member
redefine variable clocks_per_pll as a struct member
If there are multiple PLL clock nodes, this variable will
get overwritten. Redefined it as a struct member can avoid this.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I892993ffaf046f333c564170a5cac7c845ef9ba8
Reviewed-on: http://git.am.freescale.net:8181/21873
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk-qoriq.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index 6be6930..c674bbf 100644 --- a/drivers/clk/clk-qoriq.c +++ b/drivers/clk/clk-qoriq.c @@ -20,6 +20,7 @@ struct cmux_clk { struct clk_hw hw; void __iomem *reg; u32 flags; + unsigned int num_parents; }; #define PLL_KILL BIT(31) @@ -28,14 +29,13 @@ struct cmux_clk { #define to_cmux_clk(p) container_of(p, struct cmux_clk, hw) static void __iomem *base; -static unsigned int clocks_per_pll; static int cmux_set_parent(struct clk_hw *hw, u8 idx) { struct cmux_clk *clk = to_cmux_clk(hw); u32 clksel; - clksel = ((idx / clocks_per_pll) << 2) + idx % clocks_per_pll; + clksel = ((idx / clk->num_parents) << 2) + idx % clk->num_parents; if (clk->flags & CLKSEL_ADJUST) clksel += 8; clksel = (clksel & 0xf) << CLKSEL_SHIFT; @@ -53,7 +53,7 @@ static u8 cmux_get_parent(struct clk_hw *hw) clksel = (clksel >> CLKSEL_SHIFT) & 0xf; if (clk->flags & CLKSEL_ADJUST) clksel -= 8; - clksel = (clksel >> 2) * clocks_per_pll + clksel % 4; + clksel = (clksel >> 2) * clk->num_parents + clksel % 4; return clksel; } @@ -101,6 +101,7 @@ static void __init core_mux_init(struct device_node *np) goto err_name; } cmux_clk->reg = base + offset; + cmux_clk->num_parents = count; node = of_find_compatible_node(NULL, NULL, "fsl,p4080-clockgen"); if (node && (offset >= 0x80)) @@ -177,9 +178,6 @@ static void __init core_pll_init(struct device_node *np) return; } - /* output clock number per PLL */ - clocks_per_pll = count; - subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); if (!subclks) { pr_err("%s: could not allocate subclks\n", __func__); |