diff options
| author | Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> | 2014-03-21 08:47:42 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-03-21 14:07:02 (GMT) |
| commit | ad9b34062e5234df48ad1774543518268b2b929f (patch) | |
| tree | d64437a042cf09a59dc03c02dc694635f2692dfa /drivers/cpufreq | |
| parent | d81e4fdda513f875e1444e63623aa4b6e823abec (diff) | |
| download | linux-fsl-qoriq-ad9b34062e5234df48ad1774543518268b2b929f.tar.xz | |
cpufreq: powerpc: add cpufreq transition latency for FSL e500mc Socs
According to the data provided by HW Team, at least 12 internal platform
clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs.
This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition
latency to make DFS governors work normally on Freescale e500mc boards.
Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
Change-Id: Ia86f8c0f49571d697642fe7c4b98e0e9bfe92c03
Reviewed-on: http://git.am.freescale.net:8181/10024
Reviewed-by: Yang Li <LeoLi@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'drivers/cpufreq')
| -rw-r--r-- | drivers/cpufreq/ppc-corenet-cpufreq.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c b/drivers/cpufreq/ppc-corenet-cpufreq.c index 3f7be46..28adc40 100644 --- a/drivers/cpufreq/ppc-corenet-cpufreq.c +++ b/drivers/cpufreq/ppc-corenet-cpufreq.c @@ -214,7 +214,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy) for_each_cpu(i, per_cpu(cpu_mask, cpu)) per_cpu(cpu_data, i) = data; - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + policy->cpuinfo.transition_latency = + (12 * NSEC_PER_SEC) / fsl_get_sys_freq(); of_node_put(np); return 0; |