diff options
| author | Sean Paul <seanpaul@chromium.org> | 2012-07-20 20:58:59 (GMT) |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2012-08-07 06:55:52 (GMT) |
| commit | f7093f3e7a50bfeeceb8950f9130cbf8af74bf92 (patch) | |
| tree | fb3c74f8c80edf4f831cd1bc49d8cfa4cb7b149e /drivers/gpio/gpio-samsung.c | |
| parent | 5230f8fe9ad870ac24f23bca496347b87185c7c5 (diff) | |
| download | linux-fsl-qoriq-f7093f3e7a50bfeeceb8950f9130cbf8af74bf92.tar.xz | |
gpio: samsung: Fix off-by-one bug in gpio addresses
Move gpc4 to the end of the automatically processed gpio controllers so
we don't taint the automatic offset calculation.
This bug caused all controllers coming after gpc4 to map to the
incorrect address. The result is <&gpd1 0 0 0 0> would actually map to
GPIO 0 in gpd0.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Doug Anderson <dianders@chromium.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-samsung.c')
| -rw-r--r-- | drivers/gpio/gpio-samsung.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c index 92f7b2b..ba126cc 100644 --- a/drivers/gpio/gpio-samsung.c +++ b/drivers/gpio/gpio-samsung.c @@ -2454,12 +2454,6 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = { }, }, { .chip = { - .base = EXYNOS5_GPC4(0), - .ngpio = EXYNOS5_GPIO_C4_NR, - .label = "GPC4", - }, - }, { - .chip = { .base = EXYNOS5_GPD0(0), .ngpio = EXYNOS5_GPIO_D0_NR, .label = "GPD0", @@ -2513,6 +2507,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = { .label = "GPY6", }, }, { + .chip = { + .base = EXYNOS5_GPC4(0), + .ngpio = EXYNOS5_GPIO_C4_NR, + .label = "GPC4", + }, + }, { .config = &samsung_gpio_cfgs[9], .irq_base = IRQ_EINT(0), .chip = { @@ -2836,7 +2836,7 @@ static __init void exynos5_gpiolib_init(void) } /* need to set base address for gpc4 */ - exynos5_gpios_1[11].base = gpio_base1 + 0x2E0; + exynos5_gpios_1[20].base = gpio_base1 + 0x2E0; /* need to set base address for gpx */ chip = &exynos5_gpios_1[21]; |