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authorChris Wilson <chris@chris-wilson.co.uk>2010-10-01 11:05:06 (GMT)
committerChris Wilson <chris@chris-wilson.co.uk>2010-10-01 13:47:12 (GMT)
commitdc96e9b8e37641d9d15a8a4cdd18ed7680d8f546 (patch)
tree5d410cf8a1df84a73380d4fad3c76d725b7adee9 /drivers/gpu/drm/i915/i915_drv.c
parent069efc1dac477a4a51e42c0fe50bdcf85ada626a (diff)
downloadlinux-fsl-qoriq-dc96e9b8e37641d9d15a8a4cdd18ed7680d8f546.tar.xz
drm/i915: Try to reset gen2 devices.
So far only found registers for i830, i845, i865 and one of those has no effect on i865! At this moment in time, attempting to reset i8xx is a little optimistic... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.c')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2109537..f3243a3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -342,6 +342,36 @@ int i915_resume(struct drm_device *dev)
return 0;
}
+static int i8xx_do_reset(struct drm_device *dev, u8 flags)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (IS_I85X(dev))
+ return -ENODEV;
+
+ I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
+ POSTING_READ(D_STATE);
+
+ if (IS_I830(dev) || IS_845G(dev)) {
+ I915_WRITE(DEBUG_RESET_I830,
+ DEBUG_RESET_DISPLAY |
+ DEBUG_RESET_RENDER |
+ DEBUG_RESET_FULL);
+ POSTING_READ(DEBUG_RESET_I830);
+ msleep(1);
+
+ I915_WRITE(DEBUG_RESET_I830, 0);
+ POSTING_READ(DEBUG_RESET_I830);
+ }
+
+ msleep(1);
+
+ I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
+ POSTING_READ(D_STATE);
+
+ return 0;
+}
+
static int i965_reset_complete(struct drm_device *dev)
{
u8 gdrst;
@@ -410,6 +440,9 @@ int i915_reset(struct drm_device *dev, u8 flags)
case 4:
ret = i965_do_reset(dev, flags);
break;
+ case 2:
+ ret = i8xx_do_reset(dev, flags);
+ break;
}
if (ret) {
DRM_ERROR("Failed to reset chip.\n");