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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-18 15:42:10 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-18 19:22:32 (GMT) |
| commit | 1eb8dfec8dea44610dbaceea0151b3d1a8591fde (patch) | |
| tree | 9d1e98fb9b96227855d86b3697693b6c36e3d12f /drivers/gpu/drm/i915/intel_dp.c | |
| parent | a836bdf9ae5aa3b100c8cdd04aae5bb9c0340145 (diff) | |
| download | linux-fsl-qoriq-1eb8dfec8dea44610dbaceea0151b3d1a8591fde.tar.xz | |
drm/i915: fix Haswell DP M/N registers
We have to write the correct values inside intel_dp_set_m_n and then
prevent these values from being overwritten later.
V2: Unconfuse double negation.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c875e2e..db6ef13 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -816,7 +816,12 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, intel_dp_compute_m_n(intel_crtc->bpp, lane_count, mode->clock, adjusted_mode->clock, &m_n); - if (HAS_PCH_SPLIT(dev)) { + if (IS_HASWELL(dev)) { + I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); + I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); + I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); + I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); + } else if (HAS_PCH_SPLIT(dev)) { I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |