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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-11-02 09:30:46 (GMT) |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-04 09:39:50 (GMT) |
| commit | 16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c (patch) | |
| tree | 8a4d083794272b7d7bf82aad75076a7722164b23 /drivers/gpu/drm/i915 | |
| parent | 8d0f56708292ca5c256ee3b7187d124afee81d93 (diff) | |
| download | linux-fsl-qoriq-16a02cf08a2de0863daf7ebb91718d7c6bbe7f9c.tar.xz | |
agp/intel: fix cache control for sandybridge
This is broken from 97ef1bdd0bc75bce7b2058e9c432b6c277dcf4d3.
Let's set the correct bit for LLC+MLC and LLC only.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915')
0 files changed, 0 insertions, 0 deletions