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| author | Ben Skeggs <bskeggs@redhat.com> | 2013-05-13 08:29:02 (GMT) |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-07-01 03:50:40 (GMT) |
| commit | 58ef23056ae0bc060086f71ad04254e188a30ff0 (patch) | |
| tree | e7f95debc473ab3ef691dd40f1149931ea90d5a2 /drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c | |
| parent | 8b637ae3a3d8142db23eed3100245c2a2390358b (diff) | |
| download | linux-fsl-qoriq-58ef23056ae0bc060086f71ad04254e188a30ff0.tar.xz | |
drm/nvc1/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c index 27e97c0..f98d087 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c @@ -1327,6 +1327,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: case 0xc3: + case 0xc1: case 0xd9: case 0xd7: break; @@ -1475,6 +1476,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -1496,6 +1498,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x4040d0, 0x00000000); @@ -1524,6 +1527,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x404174, 0x00000000); break; @@ -1709,6 +1713,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -1771,7 +1776,6 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x408900, 0x3080b801); nv_wr32(priv, 0x408904, 0x62000001); nv_wr32(priv, 0x408908, 0x00c80929); - nv_wr32(priv, 0x40890c, 0x00000000); break; case 0xd9: case 0xd7: @@ -1806,6 +1810,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418408, 0x00000000); break; @@ -1819,6 +1824,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418414, 0x00200fff); break; @@ -1844,6 +1850,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x41870c, 0x07c80000); break; @@ -1856,6 +1863,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418800, 0x0006860a); break; @@ -1917,6 +1925,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x418b00, 0x00000000); break; @@ -1986,6 +1995,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) case 0xc0: break; case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x419a1c, 0x00000000); nv_wr32(priv, 0x419a20, 0x00000800); @@ -2000,6 +2010,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x00419ac4, 0x0017f440); break; case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x00419ac4, 0x0007f440); break; @@ -2031,6 +2042,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x419c00, 0x00000002); break; @@ -2040,6 +2052,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419c20, 0x00000000); switch (nv_device(priv)->chipset) { case 0xc3: + case 0xc1: case 0xce: case 0xcf: nv_wr32(priv, 0x419cb0, 0x00020048); @@ -2115,6 +2128,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419ee0, 0x00010110); break; case 0xc3: + case 0xc1: default: nv_wr32(priv, 0x419ee0, 0x00011110); break; @@ -2126,6 +2140,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419f54, 0x00000000); break; case 0xc3: + case 0xc1: case 0xd9: case 0xd7: nv_wr32(priv, 0x419f30, 0x00000000); @@ -2463,6 +2478,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: default: break; } @@ -2482,6 +2498,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) break; case 0xc0: case 0xc3: + case 0xc1: break; default: break; @@ -3049,11 +3066,13 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x00000585, 0x0000003f); nv_icmd(priv, 0x00000576, 0x00000003); switch (nv_device(priv)->chipset) { + case 0xc1: case 0xd9: case 0xd7: nv_icmd(priv, 0x0000057b, 0x00000059); break; case 0xc0: + case 0xc3: default: break; } @@ -3163,6 +3182,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x0000097d, 0x00000020); break; case 0xc0: + case 0xc3: + case 0xc1: default: break; } @@ -3311,6 +3332,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv) switch (nv_device(priv)->chipset) { case 0xc0: case 0xc3: + case 0xc1: nv_mthd(priv, 0x902d, 0x3410, 0x00000000); break; case 0xd9: |