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author | Ben Skeggs <bskeggs@redhat.com> | 2013-07-05 00:26:20 (GMT) |
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committer | Ben Skeggs <bskeggs@redhat.com> | 2013-07-05 03:44:52 (GMT) |
commit | d196e16ebf8bc9489ee3dc41dc5dfd84a70cec18 (patch) | |
tree | 6dfd266b79ce92b5ec62a7452f2906071e2a6aa4 /drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c | |
parent | 0bfd6f734a99ce2c7217571c45c2456ae1da63c3 (diff) | |
download | linux-fsl-qoriq-d196e16ebf8bc9489ee3dc41dc5dfd84a70cec18.tar.xz |
drm/nvc0-/gr: factor out yet more unknown magic into versioned functions
NVC1/NVD9 are the only chipsets that should have anything different
happen on them after this. We previously weren't doing these
register modifications, and NVIDIA do.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c index 118b54b..b80723e 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c @@ -901,6 +901,11 @@ nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) } void +nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv) +{ +} + +void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv) { int gpc, tpc, id; @@ -1060,6 +1065,7 @@ nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) nv_wr32(priv, 0x404154, 0x00000000); oclass->mods(priv, info); + oclass->unkn(priv); nvc0_grctx_generate_tpcid(priv); nvc0_grctx_generate_r406028(priv); @@ -1235,6 +1241,7 @@ nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { }, .main = nvc0_grctx_generate_main, .mods = nvc0_grctx_generate_mods, + .unkn = nvc0_grctx_generate_unkn, .hub = nvc0_grctx_init_hub, .gpc = nvc0_grctx_init_gpc, .icmd = nvc0_grctx_init_icmd, |