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| author | Ben Skeggs <bskeggs@redhat.com> | 2013-05-07 04:30:52 (GMT) |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2013-07-01 03:50:37 (GMT) |
| commit | 1dd44acfab048893b7f8028d63fe82df483bc5a8 (patch) | |
| tree | 1636b0fabf38d51a607cc04f00df47396b25e258 /drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c | |
| parent | a8004a9edd8c6ee86c3e263c9082ddf64797a667 (diff) | |
| download | linux-fsl-qoriq-1dd44acfab048893b7f8028d63fe82df483bc5a8.tar.xz | |
drm/nve4/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c | 74 |
1 files changed, 3 insertions, 71 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c index 574a1de..848570b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c @@ -749,38 +749,6 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x000841, 0x08000080); nv_icmd(priv, 0x000842, 0x00400008); nv_icmd(priv, 0x000843, 0x08000080); - switch (nv_device(priv)->chipset) { - case 0xe7: - case 0xe6: - break; - default: - nv_icmd(priv, 0x000818, 0x00000000); - nv_icmd(priv, 0x000819, 0x00000000); - nv_icmd(priv, 0x00081a, 0x00000000); - nv_icmd(priv, 0x00081b, 0x00000000); - nv_icmd(priv, 0x00081c, 0x00000000); - nv_icmd(priv, 0x00081d, 0x00000000); - nv_icmd(priv, 0x00081e, 0x00000000); - nv_icmd(priv, 0x00081f, 0x00000000); - nv_icmd(priv, 0x000848, 0x00000000); - nv_icmd(priv, 0x000849, 0x00000000); - nv_icmd(priv, 0x00084a, 0x00000000); - nv_icmd(priv, 0x00084b, 0x00000000); - nv_icmd(priv, 0x00084c, 0x00000000); - nv_icmd(priv, 0x00084d, 0x00000000); - nv_icmd(priv, 0x00084e, 0x00000000); - nv_icmd(priv, 0x00084f, 0x00000000); - nv_icmd(priv, 0x000850, 0x00000000); - nv_icmd(priv, 0x000851, 0x00000000); - nv_icmd(priv, 0x000852, 0x00000000); - nv_icmd(priv, 0x000853, 0x00000000); - nv_icmd(priv, 0x000854, 0x00000000); - nv_icmd(priv, 0x000855, 0x00000000); - nv_icmd(priv, 0x000856, 0x00000000); - nv_icmd(priv, 0x000857, 0x00000000); - nv_icmd(priv, 0x000738, 0x00000000); - break; - } nv_icmd(priv, 0x0006aa, 0x00000001); nv_icmd(priv, 0x0006ab, 0x00000002); nv_icmd(priv, 0x0006ac, 0x00000080); @@ -869,38 +837,6 @@ nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv) nv_icmd(priv, 0x000813, 0x00000006); nv_icmd(priv, 0x000814, 0x00000008); nv_icmd(priv, 0x000957, 0x00000003); - switch (nv_device(priv)->chipset) { - case 0xe7: - case 0xe6: - break; - default: - nv_icmd(priv, 0x000818, 0x00000000); - nv_icmd(priv, 0x000819, 0x00000000); - nv_icmd(priv, 0x00081a, 0x00000000); - nv_icmd(priv, 0x00081b, 0x00000000); - nv_icmd(priv, 0x00081c, 0x00000000); - nv_icmd(priv, 0x00081d, 0x00000000); - nv_icmd(priv, 0x00081e, 0x00000000); - nv_icmd(priv, 0x00081f, 0x00000000); - nv_icmd(priv, 0x000848, 0x00000000); - nv_icmd(priv, 0x000849, 0x00000000); - nv_icmd(priv, 0x00084a, 0x00000000); - nv_icmd(priv, 0x00084b, 0x00000000); - nv_icmd(priv, 0x00084c, 0x00000000); - nv_icmd(priv, 0x00084d, 0x00000000); - nv_icmd(priv, 0x00084e, 0x00000000); - nv_icmd(priv, 0x00084f, 0x00000000); - nv_icmd(priv, 0x000850, 0x00000000); - nv_icmd(priv, 0x000851, 0x00000000); - nv_icmd(priv, 0x000852, 0x00000000); - nv_icmd(priv, 0x000853, 0x00000000); - nv_icmd(priv, 0x000854, 0x00000000); - nv_icmd(priv, 0x000855, 0x00000000); - nv_icmd(priv, 0x000856, 0x00000000); - nv_icmd(priv, 0x000857, 0x00000000); - nv_icmd(priv, 0x000738, 0x00000000); - break; - } nv_icmd(priv, 0x000b07, 0x00000002); nv_icmd(priv, 0x000b08, 0x00000100); nv_icmd(priv, 0x000b09, 0x00000100); @@ -2180,6 +2116,7 @@ nve0_grctx_generate_902d(struct nvc0_graph_priv *priv) case 0xe6: nv_mthd(priv, 0x902d, 0x3410, 0x80002006); break; + case 0xe4: case 0xe7: default: nv_mthd(priv, 0x902d, 0x3410, 0x00000000); @@ -2716,6 +2653,7 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419e94, 0x0); nv_wr32(priv, 0x419e98, 0x0); switch (nv_device(priv)->chipset) { + case 0xe4: case 0xe7: case 0xe6: nv_wr32(priv, 0x419eac, 0x1f8f); @@ -2726,10 +2664,6 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419eb0, 0xdb00da0); nv_wr32(priv, 0x419eb8, 0x0); break; - default: - nv_wr32(priv, 0x419eac, 0x1fcf); - nv_wr32(priv, 0x419eb0, 0xd3f); - break; } nv_wr32(priv, 0x419ec8, 0x1304f); nv_wr32(priv, 0x419f30, 0x0); @@ -2749,6 +2683,7 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419f4c, 0x0); nv_wr32(priv, 0x419f58, 0x0); switch (nv_device(priv)->chipset) { + case 0xe4: case 0xe7: case 0xe6: nv_wr32(priv, 0x419f70, 0x0); @@ -2760,9 +2695,6 @@ nve0_graph_generate_tpc(struct nvc0_graph_priv *priv) nv_wr32(priv, 0x419f78, 0xeb); nv_wr32(priv, 0x419f7c, 0x404); break; - default: - nv_wr32(priv, 0x419f78, 0xb); - break; } } |