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author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-19 22:17:34 (GMT) |
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committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-03 03:12:56 (GMT) |
commit | ebb945a94bba2ce8dff7b0942ff2b3f2a52a0a69 (patch) | |
tree | 07cad59be501458e6ae1304b7c0352e322ac3387 /drivers/gpu/drm/nouveau/nv04_display.c | |
parent | ac1499d9573f4aadd1d2beac11fe23af8ce90c24 (diff) | |
download | linux-fsl-qoriq-ebb945a94bba2ce8dff7b0942ff2b3f2a52a0a69.tar.xz |
drm/nouveau: port all engines to new engine module format
This is a HUGE commit, but it's not nearly as bad as it looks - any problems
can be isolated to a particular chipset and engine combination. It was
simply too difficult to port each one at a time, the compat layers are
*already* ridiculous.
Most of the changes here are simply to the glue, the process for each of the
engine modules was to start with a standard skeleton and copy+paste the old
code into the appropriate places, fixing up variable names etc as needed.
v2: Marcin Slusarz <marcin.slusarz@gmail.com>
- fix find/replace bug in license header
v3: Ben Skeggs <bskeggs@redhat.com>
- bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and
left no space for kernel's requirements during GEM pushbuf submission.
- fix duplicate assignments noticed by clang
v4: Marcin Slusarz <marcin.slusarz@gmail.com>
- add sparse annotations to nv04_fifo_pause/nv04_fifo_start
- use ioread32_native/iowrite32_native for fifo control registers
v5: Ben Skeggs <bskeggs@redhat.com>
- rebase on v3.6-rc4, modified to keep copy engine fix intact
- nv10/fence: unmap fence bo before destroying
- fixed fermi regression when using nvidia gr fuc
- fixed typo in supported dma_mask checking
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_display.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_display.c | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c index 81947ea..6ab9363 100644 --- a/drivers/gpu/drm/nouveau/nv04_display.c +++ b/drivers/gpu/drm/nouveau/nv04_display.c @@ -32,9 +32,6 @@ #include "nouveau_encoder.h" #include "nouveau_connector.h" -static void nv04_vblank_crtc0_isr(struct drm_device *); -static void nv04_vblank_crtc1_isr(struct drm_device *); - int nv04_display_early_init(struct drm_device *dev) { @@ -126,8 +123,6 @@ nv04_display_create(struct drm_device *dev) func->save(encoder); } - nouveau_irq_register(dev, 24, nv04_vblank_crtc0_isr); - nouveau_irq_register(dev, 25, nv04_vblank_crtc1_isr); return 0; } @@ -141,9 +136,6 @@ nv04_display_destroy(struct drm_device *dev) NV_DEBUG_KMS(dev, "\n"); - nouveau_irq_unregister(dev, 24); - nouveau_irq_unregister(dev, 25); - /* Turn every CRTC off. */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct drm_mode_set modeset = { @@ -203,17 +195,3 @@ nv04_display_fini(struct drm_device *dev) if (nv_two_heads(dev)) NVWriteCRTC(dev, 1, NV_PCRTC_INTR_EN_0, 0); } - -static void -nv04_vblank_crtc0_isr(struct drm_device *dev) -{ - nv_wr32(dev, NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK); - drm_handle_vblank(dev, 0); -} - -static void -nv04_vblank_crtc1_isr(struct drm_device *dev) -{ - nv_wr32(dev, NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK); - drm_handle_vblank(dev, 1); -} |