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authorDave Airlie <airlied@redhat.com>2009-12-01 06:04:56 (GMT)
committerDave Airlie <airlied@redhat.com>2009-12-02 04:00:13 (GMT)
commit1614f8b17b8cc3ad143541d41569623d30dbc9ec (patch)
tree7b0284e942cb68ea47cdc832bbd43864b23dcd2d /drivers/gpu/drm/radeon/radeon.h
parentd8f60cfc93452d0554f6a701aa8e3236cbee4636 (diff)
downloadlinux-fsl-qoriq-1614f8b17b8cc3ad143541d41569623d30dbc9ec.tar.xz
drm/radeon/kms: add irq mitigation code for sw interrupt.
We really don't need to process every irq that comes in, we only really want to do SW irq processing when we are actually waiting for a fence to pass. I'm not 100% sure this is race free esp on non-MSI systems so it needs some testing. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 0b8dad6..bdad153 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -352,11 +352,14 @@ struct radeon_irq {
bool sw_int;
/* FIXME: use a define max crtc rather than hardcode it */
bool crtc_vblank_int[2];
+ spinlock_t sw_lock;
+ int sw_refcount;
};
int radeon_irq_kms_init(struct radeon_device *rdev);
void radeon_irq_kms_fini(struct radeon_device *rdev);
-
+void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
+void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
/*
* CP & ring.