diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2012-10-08 21:46:27 (GMT) |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2012-10-15 17:21:02 (GMT) |
| commit | 3691feea9826771d853d28d37b6b6e34758fa66d (patch) | |
| tree | 5000b982be2ea7b4ec4dc4290245d4a0fd4a9c2b /drivers/gpu/drm/radeon | |
| parent | c1a7ca0de38c23a15f652b1693afd56c9f07b16c (diff) | |
| download | linux-fsl-qoriq-3691feea9826771d853d28d37b6b6e34758fa66d.tar.xz | |
drm/radeon: check if pcie gen 2 is already enabled (v2)
If so, skip enabling it to save time.
v2: coding style fixes
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 6 |
2 files changed, 12 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index a1f49c5..14313ad 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -3431,9 +3431,14 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev) if (!(mask & DRM_PCIE_SPEED_50)) return; + speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); + if (speed_cntl & LC_CURRENT_DATA_RATE) { + DRM_INFO("PCIE gen 2 link speeds already enabled\n"); + return; + } + DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); - speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 70c800f..cda280d 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -3703,6 +3703,12 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev) if (!(mask & DRM_PCIE_SPEED_50)) return; + speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); + if (speed_cntl & LC_CURRENT_DATA_RATE) { + DRM_INFO("PCIE gen 2 link speeds already enabled\n"); + return; + } + DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); /* 55 nm r6xx asics */ |