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authorJesse Barnes <jbarnes@virtuousgeek.org>2012-10-25 19:15:48 (GMT)
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-11-11 22:51:37 (GMT)
commit310c53a84f592d3e4a54dc26d512d1429695080b (patch)
tree237998ad5e41f52d4db0fedc46e403e9209b79aa /drivers/gpu/drm
parent3ac7831314eba873d60b58718123c503f6961337 (diff)
downloadlinux-fsl-qoriq-310c53a84f592d3e4a54dc26d512d1429695080b.tar.xz
drm/i915: add clock gating regs to VLV offset check function
So we can write them properly. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Antti Koskipää <antti.koskipaa@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5138563..a08e9ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1133,8 +1133,17 @@ static bool IS_DISPLAYREG(u32 reg)
return false;
switch (reg) {
+ case _3D_CHICKEN3:
+ case IVB_CHICKEN3:
+ case GEN7_COMMON_SLICE_CHICKEN1:
+ case GEN7_L3CNTLREG1:
+ case GEN7_L3_CHICKEN_MODE_REGISTER:
case GEN7_ROW_CHICKEN2:
+ case GEN7_L3SQCREG4:
+ case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
case GEN7_HALF_SLICE_CHICKEN1:
+ case GEN6_MBCTL:
+ case GEN6_UCGCTL2:
return false;
default:
break;