diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-09-24 18:26:24 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-10 10:46:52 (GMT) |
| commit | 27e639bf024a0706015dbb348eb32619a9bb9329 (patch) | |
| tree | 3600c170f85006fbf5b6f246887fd9f8dd3d6308 /drivers/gpu | |
| parent | c1a9ae43885246df7a35c790960d7a703b2841d4 (diff) | |
| download | linux-fsl-qoriq-27e639bf024a0706015dbb348eb32619a9bb9329.tar.xz | |
drm/i915: Make sure we respect n.max on VLV
We limit the maximum n divider value in order to make sure the PLL's
reference inout is at least 19.2 MHz. I assume that is done to satisfy
some hardware requirement.
However we never check whether that calculated limit is below the
maximum supoorted N divider value (7). In practice that is always true
since we only support 100 MHz reference clock, but making the code
safe against higher reference clocks seems like a reasoanble thing to
do.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 62cfada..ed95eb2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -678,15 +678,16 @@ vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, intel_clock_t *best_clock) { intel_clock_t clock; - u32 minupdate = 19200; unsigned int bestppm = 1000000; + /* min update 19.2 MHz */ + int max_n = min(limit->n.max, refclk / 19200); target *= 5; /* fast clock */ memset(best_clock, 0, sizeof(*best_clock)); /* based on hardware requirement, prefer smaller n to precision */ - for (clock.n = limit->n.min; clock.n <= ((refclk) / minupdate); clock.n++) { + for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { for (clock.p1 = limit->p1.max; clock.p1 > limit->p1.min; clock.p1--) { for (clock.p2 = limit->p2.p2_fast; clock.p2 > 0; clock.p2 -= clock.p2 > 10 ? 2 : 1) { |