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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-10-07 23:01:20 (GMT)
committerChris Wilson <chris@chris-wilson.co.uk>2010-10-08 09:28:25 (GMT)
commit8088699f029b2a27af9bc5431ef7542c84195760 (patch)
treeb60576f4b02512c6d7852bcb1e9afba21eaa7c23 /drivers/gpu
parent17f6766c622e03a938f767b49399a68107aef537 (diff)
downloadlinux-fsl-qoriq-8088699f029b2a27af9bc5431ef7542c84195760.tar.xz
drm/i915: don't program FDI RX/TX in mode_set
We do this later (and more properly) when we enable FDI, so we don't need to do it here. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c21
1 files changed, 0 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 29ecaa0..89cfe46 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4140,27 +4140,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
ironlake_set_pll_edp(crtc, adjusted_mode->clock);
- } else {
- /* enable FDI RX PLL too */
- reg = FDI_RX_CTL(pipe);
- temp = I915_READ(reg);
- I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
-
- POSTING_READ(reg);
- udelay(200);
-
- /* enable FDI TX PLL too */
- reg = FDI_TX_CTL(pipe);
- temp = I915_READ(reg);
- I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
-
- /* enable FDI RX PCDCLK */
- reg = FDI_RX_CTL(pipe);
- temp = I915_READ(reg);
- I915_WRITE(reg, temp | FDI_PCDCLK);
-
- POSTING_READ(reg);
- udelay(200);
}
}