Merge branch 'b4860rev2'

2 files changed, 86 insertions, 22 deletions

diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c
index 4d466d6..84a5de7 100644
--- a/drivers/iommu/fsl_pamu.c
+++ b/drivers/iommu/fsl_pamu.c
@@ -32,6 +32,7 @@
 #include <asm/io.h>
 #include <asm/bitops.h>
 #include <asm/fsl_guts.h>
+#include <asm/fsl_kibo.h>
 
 #include "fsl_pamu.h"
 
@@ -529,6 +530,72 @@ void get_ome_index(u32 *omi_index, struct device *dev)
 		*omi_index = OMI_QMAN_PRIV;
 }
 
+/*
+ * We get the stash id programmed by SDOS from the shared
+ * cluster L2 l2csr1 register.
+ */
+static u32 get_dsp_l2_stash_id(u32 cluster)
+{
+	const u32 *prop;
+	struct device_node *node;
+	struct device_node *dsp_cpu_node;
+	struct ccsr_cluster_l2 *l2cache_regs;
+	u32 stash_id;
+
+	for_each_compatible_node(node, NULL, "fsl,sc3900-cluster") {
+		prop = of_get_property(node, "reg", 0);
+		if (!prop) {
+			pr_err("missing reg property in dsp cluster %s\n",
+				node->full_name);
+			of_node_put(node);
+			return ~(u32)0;
+		}
+
+		if (*prop == cluster) {
+			dsp_cpu_node = of_find_compatible_node(node, NULL, "fsl,sc3900");
+			if (!dsp_cpu_node) {
+				pr_err("missing dsp cpu node in dsp cluster %s\n",
+					node->full_name);
+				of_node_put(node);
+				return ~(u32)0;
+			}
+			of_node_put(node);
+
+			prop = of_get_property(dsp_cpu_node, "next-level-cache", 0);
+			if (!prop) {
+				pr_err("missing next level cache property in dsp cpu %s\n",
+					node->full_name);
+				of_node_put(dsp_cpu_node);
+				return ~(u32)0;
+			}
+			of_node_put(dsp_cpu_node);
+
+			node = of_find_node_by_phandle(*prop);
+			if (!node) {
+				pr_err("Invalid node for cache hierarchy %s\n",
+					node->full_name);
+				return ~(u32)0;
+			}
+
+			l2cache_regs = of_iomap(node, 0);
+			if (!l2cache_regs) {
+				pr_err("failed to map cluster l2 cache registers %s\n",
+					node->full_name);
+				of_node_put(node);
+				return ~(u32)0;
+			}
+
+			stash_id = in_be32(&l2cache_regs->l2csr1) &
+					 CLUSTER_L2_STASH_MASK;
+			of_node_put(node);
+			iounmap(l2cache_regs);
+
+			return stash_id;
+		}
+	}
+	return ~(u32)0;
+}
+
 /**
  * get_stash_id - Returns stash destination id corresponding to a
  *                cache type and vcpu.
@@ -546,6 +613,10 @@ u32 get_stash_id(u32 stash_dest_hint, u32 vcpu)
 	int len, found = 0;
 	int i;
 
+	/* check for DSP L2 cache */
+	if (stash_dest_hint == IOMMU_ATTR_CACHE_DSP_L2) {
+		return get_dsp_l2_stash_id(vcpu);
+	}
 	/* Fastpath, exit early if L3/CPC cache is target for stashing */
 	if (stash_dest_hint == IOMMU_ATTR_CACHE_L3) {
 		node = of_find_matching_node(NULL, l3_device_ids);
@@ -707,26 +778,12 @@ static void __init setup_omt(struct ome *omt)
 	ome->moe[IOE_DIRECT0_IDX] = EOE_LDEC | EOE_VALID;
 	ome->moe[IOE_DIRECT1_IDX] = EOE_LDEC | EOE_VALID;
 
-	/* Configure OMI_DMA */
-	ome = &omt[OMI_DMA];
-	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA;
-	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
-
-	/* Configure OMI_DMA_READI */
-	ome = &omt[OMI_DMA_READI];
-	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_READI;
-	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_READI;
-	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA;
-	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
-
-	/* Configure OMI_MAPLE */
-	ome = &omt[OMI_MAPLE];
-	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RSA;
-	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSA;
-	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSA;
+	/* Configure OMI_DSP */
+	ome = &omt[OMI_DSP];
+	ome->moe[IOE_READ_IDX]  = EOE_VALID | EOE_RWNITC;
+	ome->moe[IOE_EREAD0_IDX] = EOE_VALID | EOE_RWNITC;
+	ome->moe[IOE_WRITE_IDX] = EOE_VALID | EOE_WWSAO;
+	ome->moe[IOE_EWRITE0_IDX] = EOE_VALID | EOE_WWSAO;
 }
 
 /*
diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c
index 99c182d..b7b915e 100644
--- a/drivers/iommu/fsl_pamu_domain.c
+++ b/drivers/iommu/fsl_pamu_domain.c
@@ -800,6 +800,11 @@ static  int configure_domain_geometry(struct iommu_domain *domain, void *data)
 	return 0;
 }
 
+static inline int check_attr_window(u32 wnd, struct fsl_dma_domain *dma_domain)
+{
+	return ((~wnd != 0) && (wnd >= dma_domain->win_cnt));
+}
+
 /* Set the domain operation mapping attribute */
 static int configure_domain_op_map(struct fsl_dma_domain *dma_domain,
 				    void *data)
@@ -818,7 +823,8 @@ static int configure_domain_op_map(struct fsl_dma_domain *dma_domain,
 		return -ENODEV;
 	}
 
-	if (omi_attr->omi >= OMI_MAX) {
+	if (omi_attr->omi >= OMI_MAX ||
+		check_attr_window(omi_attr->window, dma_domain)) {
 		pr_err("Invalid operation mapping index\n");
 		spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
 		return -EINVAL;
@@ -863,7 +869,8 @@ static int configure_domain_stash(struct fsl_dma_domain *dma_domain, void *data)
 
 	stash_id = get_stash_id(stash_attr->cache,
 					    stash_attr->cpu);
-	if (~stash_id == 0) {
+	if ((~stash_id == 0) ||
+		 check_attr_window(stash_attr->window, dma_domain)) {
 		pr_err("Invalid stash attributes\n");
 		spin_unlock_irqrestore(&dma_domain->domain_lock, flags);
 		return -EINVAL;