diff options
| author | Brian Norris <computersforpeace@gmail.com> | 2011-05-31 23:31:20 (GMT) |
|---|---|---|
| committer | Artem Bityutskiy <artem.bityutskiy@intel.com> | 2011-09-11 12:01:46 (GMT) |
| commit | a0dc552951dcbb2b28a8a2ffb5fa966613e8c025 (patch) | |
| tree | 62c71971d00f60fedcb5b265614c8925493877ad /drivers/mtd/nand/nand_base.c | |
| parent | 1c3bd14bb0e10ce69761662d575d454f12070838 (diff) | |
| download | linux-fsl-qoriq-a0dc552951dcbb2b28a8a2ffb5fa966613e8c025.tar.xz | |
mtd: nand: remove NAND_BBT_SCANBYTE1AND6 option
This patch reverts most of:
commit 58373ff0afff4cc8ac40608872995f4d87eb72ec
mtd: nand: more BB Detection refactoring and dynamic scan options
According to the discussion at:
http://lists.infradead.org/pipermail/linux-mtd/2011-May/035696.html
the NAND_BBT_SCANBYTE1AND6 flag, although technically valid, can break
some existing ECC layouts that use the 6th byte in the OOB for ECC data.
Furthermore, we apparently do not need to scan both bytes 1 and 6 in
the OOB region of the devices under consideration; instead, we only need
to scan one or the other.
Thus, the NAND_BBT_SCANBYTE1AND6 flag is at best unnecessary and at
worst a regression.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com>
Diffstat (limited to 'drivers/mtd/nand/nand_base.c')
| -rw-r--r-- | drivers/mtd/nand/nand_base.c | 24 |
1 files changed, 5 insertions, 19 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index a46e9bb..bb2e24b 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -410,10 +410,11 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) else { nand_get_device(chip, mtd, FL_WRITING); - /* Write to first two pages and to byte 1 and 6 if necessary. - * If we write to more than one location, the first error - * encountered quits the procedure. We write two bytes per - * location, so we dont have to mess with 16 bit access. + /* + * Write to first two pages if necessary. If we write to more + * than one location, the first error encountered quits the + * procedure. We write two bytes per location, so we dont have + * to mess with 16 bit access. */ do { chip->ops.len = chip->ops.ooblen = 2; @@ -423,11 +424,6 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) ret = nand_do_write_oob(mtd, ofs, &chip->ops); - if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) { - chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS - & ~0x01; - ret = nand_do_write_oob(mtd, ofs, &chip->ops); - } i++; ofs += mtd->writesize; } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) && @@ -3131,16 +3127,6 @@ ident_done: *maf_id == NAND_MFR_MICRON)) chip->options |= NAND_BBT_SCAN2NDPAGE; - /* - * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6 - */ - if (!(busw & NAND_BUSWIDTH_16) && - *maf_id == NAND_MFR_STMICRO && - mtd->writesize == 2048) { - chip->options |= NAND_BBT_SCANBYTE1AND6; - chip->badblockpos = 0; - } - /* Check for AND chips with 4 page planes */ if (chip->options & NAND_4PAGE_ARRAY) chip->erase_cmd = multi_erase_cmd; |