diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-09 17:33:19 (GMT) |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-09 17:33:19 (GMT) |
| commit | ef9a61bef917e38f8e096f6df303329aed6cf467 (patch) | |
| tree | 31cfe2444d0270e77ff8ef792df11591fed6075c /drivers/mtd/nand | |
| parent | b5f0998cae3d7ea56d3d8377e46328fe972b9546 (diff) | |
| parent | 6c3b88970175e18a67eb8e55c4eba10614d0d5dc (diff) | |
| download | linux-fsl-qoriq-ef9a61bef917e38f8e096f6df303329aed6cf467.tar.xz | |
Merge tag 'for-linus-20130909' of git://git.infradead.org/linux-mtd
Pull mtd updates from David Woodhouse:
- factor out common code from MTD tests
- nand-gpio cleanup and portability to non-ARM
- m25p80 support for 4-byte addressing chips, other new chips
- pxa3xx cleanup and support for new platforms
- remove obsolete alauda, octagon-5066 drivers
- erase/write support for bcm47xxsflash
- improve detection of ECC requirements for NAND, controller setup
- NFC acceleration support for atmel-nand, read/write via SRAM
- etc
* tag 'for-linus-20130909' of git://git.infradead.org/linux-mtd: (184 commits)
mtd: chips: Add support for PMC SPI Flash chips in m25p80.c
mtd: ofpart: use for_each_child_of_node() macro
mtd: mtdswap: replace strict_strtoul() with kstrtoul()
mtd cs553x_nand: use kzalloc() instead of memset
mtd: atmel_nand: fix error return code in atmel_nand_probe()
mtd: bcm47xxsflash: writing support
mtd: bcm47xxsflash: implement erasing support
mtd: bcm47xxsflash: convert to module_platform_driver instead of init/exit
mtd: bcm47xxsflash: convert kzalloc to avoid invalid access
mtd: remove alauda driver
mtd: nand: mxc_nand: mark 'const' properly
mtd: maps: cfi_flagadm: add missing __iomem annotation
mtd: spear_smi: add missing __iomem annotation
mtd: r852: Staticize local symbols
mtd: nandsim: Staticize local symbols
mtd: impa7: add missing __iomem annotation
mtd: sm_ftl: Staticize local symbols
mtd: m25p80: add support for mr25h10
mtd: m25p80: make CONFIG_M25PXX_USE_FAST_READ safe to enable
mtd: m25p80: Pass flags through CAT25_INFO macro
...
Diffstat (limited to 'drivers/mtd/nand')
37 files changed, 1724 insertions, 1671 deletions
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 50543f1..d885298 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -43,6 +43,7 @@ config MTD_SM_COMMON config MTD_NAND_DENALI tristate "Support Denali NAND controller" + depends on HAS_DMA help Enable support for the Denali NAND controller. This should be combined with either the PCI or platform drivers to provide device @@ -75,7 +76,7 @@ config MTD_NAND_DENALI_SCRATCH_REG_ADDR config MTD_NAND_GPIO tristate "GPIO NAND Flash driver" - depends on GPIOLIB && ARM + depends on GPIOLIB help This enables a GPIO based NAND flash driver. @@ -354,7 +355,7 @@ config MTD_NAND_ATMEL config MTD_NAND_PXA3xx tristate "Support for NAND flash devices on PXA3xx" - depends on PXA3xx || ARCH_MMP + depends on PXA3xx || ARCH_MMP || PLAT_ORION help This enables the driver for the NAND flash device found on PXA3xx processors @@ -432,13 +433,6 @@ config MTD_NAND_PLATFORM devices. You will need to provide platform-specific functions via platform_data. -config MTD_ALAUDA - tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1" - depends on USB - help - These two (and possibly other) Alauda-based cardreaders for - SmartMedia and xD allow raw flash access. - config MTD_NAND_ORION tristate "NAND Flash support for Marvell Orion SoC" depends on PLAT_ORION diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index bb81891..542b568 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -obj-$(CONFIG_MTD_ALAUDA) += alauda.o obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o diff --git a/drivers/mtd/nand/alauda.c b/drivers/mtd/nand/alauda.c deleted file mode 100644 index 60a0dfd..0000000 --- a/drivers/mtd/nand/alauda.c +++ /dev/null @@ -1,723 +0,0 @@ -/* - * MTD driver for Alauda chips - * - * Copyright (C) 2007 Joern Engel <joern@logfs.org> - * - * Based on drivers/usb/usb-skeleton.c which is: - * Copyright (C) 2001-2004 Greg Kroah-Hartman (greg@kroah.com) - * and on drivers/usb/storage/alauda.c, which is: - * (c) 2005 Daniel Drake <dsd@gentoo.org> - * - * Idea and initial work by Arnd Bergmann <arnd@arndb.de> - */ -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/module.h> -#include <linux/kref.h> -#include <linux/usb.h> -#include <linux/mutex.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand_ecc.h> - -/* Control commands */ -#define ALAUDA_GET_XD_MEDIA_STATUS 0x08 -#define ALAUDA_ACK_XD_MEDIA_CHANGE 0x0a -#define ALAUDA_GET_XD_MEDIA_SIG 0x86 - -/* Common prefix */ -#define ALAUDA_BULK_CMD 0x40 - -/* The two ports */ -#define ALAUDA_PORT_XD 0x00 -#define ALAUDA_PORT_SM 0x01 - -/* Bulk commands */ -#define ALAUDA_BULK_READ_PAGE 0x84 -#define ALAUDA_BULK_READ_OOB 0x85 /* don't use, there's a chip bug */ -#define ALAUDA_BULK_READ_BLOCK 0x94 -#define ALAUDA_BULK_ERASE_BLOCK 0xa3 -#define ALAUDA_BULK_WRITE_PAGE 0xa4 -#define ALAUDA_BULK_WRITE_BLOCK 0xb4 -#define ALAUDA_BULK_RESET_MEDIA 0xe0 - -/* Address shifting */ -#define PBA_LO(pba) ((pba & 0xF) << 5) -#define PBA_HI(pba) (pba >> 3) -#define PBA_ZONE(pba) (pba >> 11) - -#define TIMEOUT HZ - -static const struct usb_device_id alauda_table[] = { - { USB_DEVICE(0x0584, 0x0008) }, /* Fujifilm DPC-R1 */ - { USB_DEVICE(0x07b4, 0x010a) }, /* Olympus MAUSB-10 */ - { } -}; -MODULE_DEVICE_TABLE(usb, alauda_table); - -struct alauda_card { - u8 id; /* id byte */ - u8 chipshift; /* 1<<chipshift total size */ - u8 pageshift; /* 1<<pageshift page size */ - u8 blockshift; /* 1<<blockshift block size */ -}; - -struct alauda { - struct usb_device *dev; - struct usb_interface *interface; - struct mtd_info *mtd; - struct alauda_card *card; - struct mutex card_mutex; - u32 pagemask; - u32 bytemask; - u32 blockmask; - unsigned int write_out; - unsigned int bulk_in; - unsigned int bulk_out; - u8 port; - struct kref kref; -}; - -static struct alauda_card alauda_card_ids[] = { - /* NAND flash */ - { 0x6e, 20, 8, 12}, /* 1 MB */ - { 0xe8, 20, 8, 12}, /* 1 MB */ - { 0xec, 20, 8, 12}, /* 1 MB */ - { 0x64, 21, 8, 12}, /* 2 MB */ - { 0xea, 21, 8, 12}, /* 2 MB */ - { 0x6b, 22, 9, 13}, /* 4 MB */ - { 0xe3, 22, 9, 13}, /* 4 MB */ - { 0xe5, 22, 9, 13}, /* 4 MB */ - { 0xe6, 23, 9, 13}, /* 8 MB */ - { 0x73, 24, 9, 14}, /* 16 MB */ - { 0x75, 25, 9, 14}, /* 32 MB */ - { 0x76, 26, 9, 14}, /* 64 MB */ - { 0x79, 27, 9, 14}, /* 128 MB */ - { 0x71, 28, 9, 14}, /* 256 MB */ - - /* MASK ROM */ - { 0x5d, 21, 9, 13}, /* 2 MB */ - { 0xd5, 22, 9, 13}, /* 4 MB */ - { 0xd6, 23, 9, 13}, /* 8 MB */ - { 0x57, 24, 9, 13}, /* 16 MB */ - { 0x58, 25, 9, 13}, /* 32 MB */ - { } -}; - -static struct alauda_card *get_card(u8 id) -{ - struct alauda_card *card; - - for (card = alauda_card_ids; card->id; card++) - if (card->id == id) - return card; - return NULL; -} - -static void alauda_delete(struct kref *kref) -{ - struct alauda *al = container_of(kref, struct alauda, kref); - - if (al->mtd) { - mtd_device_unregister(al->mtd); - kfree(al->mtd); - } - usb_put_dev(al->dev); - kfree(al); -} - -static int alauda_get_media_status(struct alauda *al, void *buf) -{ - int ret; - - mutex_lock(&al->card_mutex); - ret = usb_control_msg(al->dev, usb_rcvctrlpipe(al->dev, 0), - ALAUDA_GET_XD_MEDIA_STATUS, 0xc0, 0, 1, buf, 2, HZ); - mutex_unlock(&al->card_mutex); - return ret; -} - -static int alauda_ack_media(struct alauda *al) -{ - int ret; - - mutex_lock(&al->card_mutex); - ret = usb_control_msg(al->dev, usb_sndctrlpipe(al->dev, 0), - ALAUDA_ACK_XD_MEDIA_CHANGE, 0x40, 0, 1, NULL, 0, HZ); - mutex_unlock(&al->card_mutex); - return ret; -} - -static int alauda_get_media_signatures(struct alauda *al, void *buf) -{ - int ret; - - mutex_lock(&al->card_mutex); - ret = usb_control_msg(al->dev, usb_rcvctrlpipe(al->dev, 0), - ALAUDA_GET_XD_MEDIA_SIG, 0xc0, 0, 0, buf, 4, HZ); - mutex_unlock(&al->card_mutex); - return ret; -} - -static void alauda_reset(struct alauda *al) -{ - u8 command[] = { - ALAUDA_BULK_CMD, ALAUDA_BULK_RESET_MEDIA, 0, 0, - 0, 0, 0, 0, al->port - }; - mutex_lock(&al->card_mutex); - usb_bulk_msg(al->dev, al->bulk_out, command, 9, NULL, HZ); - mutex_unlock(&al->card_mutex); -} - -static void correct_data(void *buf, void *read_ecc, - int *corrected, int *uncorrected) -{ - u8 calc_ecc[3]; - int err; - - nand_calculate_ecc(NULL, buf, calc_ecc); - err = nand_correct_data(NULL, buf, read_ecc, calc_ecc); - if (err) { - if (err > 0) - (*corrected)++; - else - (*uncorrected)++; - } -} - -struct alauda_sg_request { - struct urb *urb[3]; - struct completion comp; -}; - -static void alauda_complete(struct urb *urb) -{ - struct completion *comp = urb->context; - - if (comp) - complete(comp); -} - -static int __alauda_read_page(struct mtd_info *mtd, loff_t from, void *buf, - void *oob) -{ - struct alauda_sg_request sg; - struct alauda *al = mtd->priv; - u32 pba = from >> al->card->blockshift; - u32 page = (from >> al->card->pageshift) & al->pagemask; - u8 command[] = { - ALAUDA_BULK_CMD, ALAUDA_BULK_READ_PAGE, PBA_HI(pba), - PBA_ZONE(pba), 0, PBA_LO(pba) + page, 1, 0, al->port - }; - int i, err; - - for (i=0; i<3; i++) - sg.urb[i] = NULL; - - err = -ENOMEM; - for (i=0; i<3; i++) { - sg.urb[i] = usb_alloc_urb(0, GFP_NOIO); - if (!sg.urb[i]) - goto out; - } - init_completion(&sg.comp); - usb_fill_bulk_urb(sg.urb[0], al->dev, al->bulk_out, command, 9, - alauda_complete, NULL); - usb_fill_bulk_urb(sg.urb[1], al->dev, al->bulk_in, buf, mtd->writesize, - alauda_complete, NULL); - usb_fill_bulk_urb(sg.urb[2], al->dev, al->bulk_in, oob, 16, - alauda_complete, &sg.comp); - - mutex_lock(&al->card_mutex); - for (i=0; i<3; i++) { - err = usb_submit_urb(sg.urb[i], GFP_NOIO); - if (err) - goto cancel; - } - if (!wait_for_completion_timeout(&sg.comp, TIMEOUT)) { - err = -ETIMEDOUT; -cancel: - for (i=0; i<3; i++) { - usb_kill_urb(sg.urb[i]); - } - } - mutex_unlock(&al->card_mutex); - -out: - usb_free_urb(sg.urb[0]); - usb_free_urb(sg.urb[1]); - usb_free_urb(sg.urb[2]); - return err; -} - -static int alauda_read_page(struct mtd_info *mtd, loff_t from, - void *buf, u8 *oob, int *corrected, int *uncorrected) -{ - int err; - - err = __alauda_read_page(mtd, from, buf, oob); - if (err) - return err; - correct_data(buf, oob+13, corrected, uncorrected); - correct_data(buf+256, oob+8, corrected, uncorrected); - return 0; -} - -static int alauda_write_page(struct mtd_info *mtd, loff_t to, void *buf, - void *oob) -{ - struct alauda_sg_request sg; - struct alauda *al = mtd->priv; - u32 pba = to >> al->card->blockshift; - u32 page = (to >> al->card->pageshift) & al->pagemask; - u8 command[] = { - ALAUDA_BULK_CMD, ALAUDA_BULK_WRITE_PAGE, PBA_HI(pba), - PBA_ZONE(pba), 0, PBA_LO(pba) + page, 32, 0, al->port - }; - int i, err; - - for (i=0; i<3; i++) - sg.urb[i] = NULL; - - err = -ENOMEM; - for (i=0; i<3; i++) { - sg.urb[i] = usb_alloc_urb(0, GFP_NOIO); - if (!sg.urb[i]) - goto out; - } - init_completion(&sg.comp); - usb_fill_bulk_urb(sg.urb[0], al->dev, al->bulk_out, command, 9, - alauda_complete, NULL); - usb_fill_bulk_urb(sg.urb[1], al->dev, al->write_out, buf,mtd->writesize, - alauda_complete, NULL); - usb_fill_bulk_urb(sg.urb[2], al->dev, al->write_out, oob, 16, - alauda_complete, &sg.comp); - - mutex_lock(&al->card_mutex); - for (i=0; i<3; i++) { - err = usb_submit_urb(sg.urb[i], GFP_NOIO); - if (err) - goto cancel; - } - if (!wait_for_completion_timeout(&sg.comp, TIMEOUT)) { - err = -ETIMEDOUT; -cancel: - for (i=0; i<3; i++) { - usb_kill_urb(sg.urb[i]); - } - } - mutex_unlock(&al->card_mutex); - -out: - usb_free_urb(sg.urb[0]); - usb_free_urb(sg.urb[1]); - usb_free_urb(sg.urb[2]); - return err; -} - -static int alauda_erase_block(struct mtd_info *mtd, loff_t ofs) -{ - struct alauda_sg_request sg; - struct alauda *al = mtd->priv; - u32 pba = ofs >> al->card->blockshift; - u8 command[] = { - ALAUDA_BULK_CMD, ALAUDA_BULK_ERASE_BLOCK, PBA_HI(pba), - PBA_ZONE(pba), 0, PBA_LO(pba), 0x02, 0, al->port - }; - u8 buf[2]; - int i, err; - - for (i=0; i<2; i++) - sg.urb[i] = NULL; - - err = -ENOMEM; - for (i=0; i<2; i++) { - sg.urb[i] = usb_alloc_urb(0, GFP_NOIO); - if (!sg.urb[i]) - goto out; - } - init_completion(&sg.comp); - usb_fill_bulk_urb(sg.urb[0], al->dev, al->bulk_out, command, 9, - alauda_complete, NULL); - usb_fill_bulk_urb(sg.urb[1], al->dev, al->bulk_in, buf, 2, - alauda_complete, &sg.comp); - - mutex_lock(&al->card_mutex); - for (i=0; i<2; i++) { - err = usb_submit_urb(sg.urb[i], GFP_NOIO); - if (err) - goto cancel; - } - if (!wait_for_completion_timeout(&sg.comp, TIMEOUT)) { - err = -ETIMEDOUT; -cancel: - for (i=0; i<2; i++) { - usb_kill_urb(sg.urb[i]); - } - } - mutex_unlock(&al->card_mutex); - -out: - usb_free_urb(sg.urb[0]); - usb_free_urb(sg.urb[1]); - return err; -} - -static int alauda_read_oob(struct mtd_info *mtd, loff_t from, void *oob) -{ - static u8 ignore_buf[512]; /* write only */ - - return __alauda_read_page(mtd, from, ignore_buf, oob); -} - -static int alauda_isbad(struct mtd_info *mtd, loff_t ofs) -{ - u8 oob[16]; - int err; - - err = alauda_read_oob(mtd, ofs, oob); - if (err) - return err; - - /* A block is marked bad if two or more bits are zero */ - return hweight8(oob[5]) >= 7 ? 0 : 1; -} - -static int alauda_bounce_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) -{ - struct alauda *al = mtd->priv; - void *bounce_buf; - int err, corrected=0, uncorrected=0; - - bounce_buf = kmalloc(mtd->writesize, GFP_KERNEL); - if (!bounce_buf) - return -ENOMEM; - - *retlen = len; - while (len) { - u8 oob[16]; - size_t byte = from & al->bytemask; - size_t cplen = min(len, mtd->writesize - byte); - - err = alauda_read_page(mtd, from, bounce_buf, oob, - &corrected, &uncorrected); - if (err) - goto out; - - memcpy(buf, bounce_buf + byte, cplen); - buf += cplen; - from += cplen; - len -= cplen; - } - err = 0; - if (corrected) - err = 1; /* return max_bitflips per ecc step */ - if (uncorrected) - err = -EBADMSG; -out: - kfree(bounce_buf); - return err; -} - -static int alauda_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) -{ - struct alauda *al = mtd->priv; - int err, corrected=0, uncorrected=0; - - if ((from & al->bytemask) || (len & al->bytemask)) - return alauda_bounce_read(mtd, from, len, retlen, buf); - - *retlen = len; - while (len) { - u8 oob[16]; - - err = alauda_read_page(mtd, from, buf, oob, - &corrected, &uncorrected); - if (err) - return err; - - buf += mtd->writesize; - from += mtd->writesize; - len -= mtd->writesize; - } - err = 0; - if (corrected) - err = 1; /* return max_bitflips per ecc step */ - if (uncorrected) - err = -EBADMSG; - return err; -} - -static int alauda_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) -{ - struct alauda *al = mtd->priv; - int err; - - if ((to & al->bytemask) || (len & al->bytemask)) - return -EINVAL; - - *retlen = len; - while (len) { - u32 page = (to >> al->card->pageshift) & al->pagemask; - u8 oob[16] = { 'h', 'e', 'l', 'l', 'o', 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - - /* don't write to bad blocks */ - if (page == 0) { - err = alauda_isbad(mtd, to); - if (err) { - return -EIO; - } - } - nand_calculate_ecc(mtd, buf, &oob[13]); - nand_calculate_ecc(mtd, buf+256, &oob[8]); - - err = alauda_write_page(mtd, to, (void*)buf, oob); - if (err) - return err; - - buf += mtd->writesize; - to += mtd->writesize; - len -= mtd->writesize; - } - return 0; -} - -static int __alauda_erase(struct mtd_info *mtd, struct erase_info *instr) -{ - struct alauda *al = mtd->priv; - u32 ofs = instr->addr; - u32 len = instr->len; - int err; - - if ((ofs & al->blockmask) || (len & al->blockmask)) - return -EINVAL; - - while (len) { - /* don't erase bad blocks */ - err = alauda_isbad(mtd, ofs); - if (err > 0) - err = -EIO; - if (err < 0) - return err; - - err = alauda_erase_block(mtd, ofs); - if (err < 0) - return err; - - ofs += mtd->erasesize; - len -= mtd->erasesize; - } - return 0; -} - -static int alauda_erase(struct mtd_info *mtd, struct erase_info *instr) -{ - int err; - - err = __alauda_erase(mtd, instr); - instr->state = err ? MTD_ERASE_FAILED : MTD_ERASE_DONE; - mtd_erase_callback(instr); - return err; -} - -static int alauda_init_media(struct alauda *al) -{ - u8 buf[4], *b0=buf, *b1=buf+1; - struct alauda_card *card; - struct mtd_info *mtd; - int err; - - mtd = kzalloc(sizeof(*mtd), GFP_KERNEL); - if (!mtd) - return -ENOMEM; - - for (;;) { - err = alauda_get_media_status(al, buf); - if (err < 0) - goto error; - if (*b0 & 0x10) - break; - msleep(20); - } - - err = alauda_ack_media(al); - if (err) - goto error; - - msleep(10); - - err = alauda_get_media_status(al, buf); - if (err < 0) - goto error; - - if (*b0 != 0x14) { - /* media not ready */ - err = -EIO; - goto error; - } - err = alauda_get_media_signatures(al, buf); - if (err < 0) - goto error; - - card = get_card(*b1); - if (!card) { - printk(KERN_ERR"Alauda: unknown card id %02x\n", *b1); - err = -EIO; - goto error; - } - printk(KERN_INFO"pagesize=%x\nerasesize=%x\nsize=%xMiB\n", - 1<<card->pageshift, 1<<card->blockshift, - 1<<(card->chipshift-20)); - al->card = card; - al->pagemask = (1 << (card->blockshift - card->pageshift)) - 1; - al->bytemask = (1 << card->pageshift) - 1; - al->blockmask = (1 << card->blockshift) - 1; - - mtd->name = "alauda"; - mtd->size = 1<<card->chipshift; - mtd->erasesize = 1<<card->blockshift; - mtd->writesize = 1<<card->pageshift; - mtd->type = MTD_NANDFLASH; - mtd->flags = MTD_CAP_NANDFLASH; - mtd->_read = alauda_read; - mtd->_write = alauda_write; - mtd->_erase = alauda_erase; - mtd->_block_isbad = alauda_isbad; - mtd->priv = al; - mtd->owner = THIS_MODULE; - mtd->ecc_strength = 1; - - err = mtd_device_register(mtd, NULL, 0); - if (err) { - err = -ENFILE; - goto error; - } - - al->mtd = mtd; - alauda_reset(al); /* no clue whether this is necessary */ - return 0; -error: - kfree(mtd); - return err; -} - -static int alauda_check_media(struct alauda *al) -{ - u8 buf[2], *b0 = buf, *b1 = buf+1; - int err; - - err = alauda_get_media_status(al, buf); - if (err < 0) - return err; - - if ((*b1 & 0x01) == 0) { - /* door open */ - return -EIO; - } - if ((*b0 & 0x80) || ((*b0 & 0x1F) == 0x10)) { - /* no media ? */ - return -EIO; - } - if (*b0 & 0x08) { - /* media change ? */ - return alauda_init_media(al); - } - return 0; -} - -static int alauda_probe(struct usb_interface *interface, - const struct usb_device_id *id) -{ - struct alauda *al; - struct usb_host_interface *iface; - struct usb_endpoint_descriptor *ep, - *ep_in=NULL, *ep_out=NULL, *ep_wr=NULL; - int i, err = -ENOMEM; - - al = kzalloc(2*sizeof(*al), GFP_KERNEL); - if (!al) - goto error; - - kref_init(&al->kref); - usb_set_intfdata(interface, al); - - al->dev = usb_get_dev(interface_to_usbdev(interface)); - al->interface = interface; - - iface = interface->cur_altsetting; - for (i = 0; i < iface->desc.bNumEndpoints; ++i) { - ep = &iface->endpoint[i].desc; - - if (usb_endpoint_is_bulk_in(ep)) { - ep_in = ep; - } else if (usb_endpoint_is_bulk_out(ep)) { - if (i==0) - ep_wr = ep; - else - ep_out = ep; - } - } - err = -EIO; - if (!ep_wr || !ep_in || !ep_out) - goto error; - - al->write_out = usb_sndbulkpipe(al->dev, - usb_endpoint_num(ep_wr)); - al->bulk_in = usb_rcvbulkpipe(al->dev, - usb_endpoint_num(ep_in)); - al->bulk_out = usb_sndbulkpipe(al->dev, - usb_endpoint_num(ep_out)); - - /* second device is identical up to now */ - memcpy(al+1, al, sizeof(*al)); - - mutex_init(&al[0].card_mutex); - mutex_init(&al[1].card_mutex); - - al[0].port = ALAUDA_PORT_XD; - al[1].port = ALAUDA_PORT_SM; - - dev_info(&interface->dev, "alauda probed\n"); - alauda_check_media(al); - alauda_check_media(al+1); - - return 0; - -error: - if (al) - kref_put(&al->kref, alauda_delete); - return err; -} - -static void alauda_disconnect(struct usb_interface *interface) -{ - struct alauda *al; - - al = usb_get_intfdata(interface); - usb_set_intfdata(interface, NULL); - - /* FIXME: prevent more I/O from starting */ - - /* decrement our usage count */ - if (al) - kref_put(&al->kref, alauda_delete); - - dev_info(&interface->dev, "alauda gone"); -} - -static struct usb_driver alauda_driver = { - .name = "alauda", - .probe = alauda_probe, - .disconnect = alauda_disconnect, - .id_table = alauda_table, -}; - -module_usb_driver(alauda_driver); - -MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c index f1d71cd..8611eb4 100644 --- a/drivers/mtd/nand/ams-delta.c +++ b/drivers/mtd/nand/ams-delta.c @@ -258,7 +258,6 @@ static int ams_delta_init(struct platform_device *pdev) out_mtd: gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio)); out_gpio: - platform_set_drvdata(pdev, NULL); gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB); iounmap(io_base); out_free: diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 2d23d29..060feea 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -18,6 +18,9 @@ * Add Programmable Multibit ECC support for various AT91 SoC * © Copyright 2012 ATMEL, Hong Xu * + * Add Nand Flash Controller support for SAMA5 SoC + * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com) + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -37,13 +40,12 @@ #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> +#include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/gpio.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/platform_data/atmel.h> -#include <linux/pinctrl/consumer.h> - -#include <mach/cpu.h> static int use_dma = 1; module_param(use_dma, int, 0); @@ -58,6 +60,7 @@ module_param(on_flash_bbt, int, 0); __raw_writel((value), add + ATMEL_ECC_##reg) #include "atmel_nand_ecc.h" /* Hardware ECC registers */ +#include "atmel_nand_nfc.h" /* Nand Flash Controller definition */ /* oob layout for large page size * bad block info is on bytes 0 and 1 @@ -85,6 +88,23 @@ static struct nand_ecclayout atmel_oobinfo_small = { }, }; +struct atmel_nfc { + void __iomem *base_cmd_regs; + void __iomem *hsmc_regs; + void __iomem *sram_bank0; + dma_addr_t sram_bank0_phys; + bool use_nfc_sram; + bool write_by_sram; + + bool is_initialized; + struct completion comp_nfc; + + /* Point to the sram bank which include readed data via NFC */ + void __iomem *data_in_sram; + bool will_write_sram; +}; +static struct atmel_nfc nand_nfc; + struct atmel_nand_host { struct nand_chip nand_chip; struct mtd_info mtd; @@ -97,6 +117,8 @@ struct atmel_nand_host { struct completion comp; struct dma_chan *dma_chan; + struct atmel_nfc *nfc; + bool has_pmecc; u8 pmecc_corr_cap; u16 pmecc_sector_size; @@ -128,11 +150,6 @@ struct atmel_nand_host { static struct nand_ecclayout atmel_pmecc_oobinfo; -static int cpu_has_dma(void) -{ - return cpu_is_at91sam9rl() || cpu_is_at91sam9g45(); -} - /* * Enable NAND. */ @@ -186,21 +203,103 @@ static int atmel_nand_device_ready(struct mtd_info *mtd) !!host->board.rdy_pin_active_low; } +/* Set up for hardware ready pin and enable pin. */ +static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct atmel_nand_host *host = chip->priv; + int res = 0; + + if (gpio_is_valid(host->board.rdy_pin)) { + res = devm_gpio_request(host->dev, + host->board.rdy_pin, "nand_rdy"); + if (res < 0) { + dev_err(host->dev, + "can't request rdy gpio %d\n", + host->board.rdy_pin); + return res; + } + + res = gpio_direction_input(host->board.rdy_pin); + if (res < 0) { + dev_err(host->dev, + "can't request input direction rdy gpio %d\n", + host->board.rdy_pin); + return res; + } + + chip->dev_ready = atmel_nand_device_ready; + } + + if (gpio_is_valid(host->board.enable_pin)) { + res = devm_gpio_request(host->dev, + host->board.enable_pin, "nand_enable"); + if (res < 0) { + dev_err(host->dev, + "can't request enable gpio %d\n", + host->board.enable_pin); + return res; + } + + res = gpio_direction_output(host->board.enable_pin, 1); + if (res < 0) { + dev_err(host->dev, + "can't request output direction enable gpio %d\n", + host->board.enable_pin); + return res; + } + } + + return res; +} + +static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) +{ + int i; + u32 *t = trg; + const __iomem u32 *s = src; + + for (i = 0; i < (size >> 2); i++) + *t++ = readl_relaxed(s++); +} + +static void memcpy32_toio(void __iomem *trg, const void *src, int size) +{ + int i; + u32 __iomem *t = trg; + const u32 *s = src; + + for (i = 0; i < (size >> 2); i++) + writel_relaxed(*s++, t++); +} + /* * Minimal-overhead PIO for data access. */ static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len) { struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; - __raw_readsb(nand_chip->IO_ADDR_R, buf, len); + if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) { + memcpy32_fromio(buf, host->nfc->data_in_sram, len); + host->nfc->data_in_sram += len; + } else { + __raw_readsb(nand_chip->IO_ADDR_R, buf, len); + } } static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len) { struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; - __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2); + if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) { + memcpy32_fromio(buf, host->nfc->data_in_sram, len); + host->nfc->data_in_sram += len; + } else { + __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2); + } } static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len) @@ -222,6 +321,40 @@ static void dma_complete_func(void *completion) complete(completion); } +static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank) +{ + /* NFC only has two banks. Must be 0 or 1 */ + if (bank > 1) + return -EINVAL; + + if (bank) { + /* Only for a 2k-page or lower flash, NFC can handle 2 banks */ + if (host->mtd.writesize > 2048) + return -EINVAL; + nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1); + } else { + nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0); + } + + return 0; +} + +static uint nfc_get_sram_off(struct atmel_nand_host *host) +{ + if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1) + return NFC_SRAM_BANK1_OFFSET; + else + return 0; +} + +static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host) +{ + if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1) + return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET; + else + return host->nfc->sram_bank0_phys; +} + static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, int is_read) { @@ -235,6 +368,7 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, void *p = buf; int err = -EIO; enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; + struct atmel_nfc *nfc = host->nfc; if (buf >= high_memory) goto err_buf; @@ -251,11 +385,20 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, } if (is_read) { - dma_src_addr = host->io_phys; + if (nfc && nfc->data_in_sram) + dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram + - (nfc->sram_bank0 + nfc_get_sram_off(host))); + else + dma_src_addr = host->io_phys; + dma_dst_addr = phys_addr; } else { dma_src_addr = phys_addr; - dma_dst_addr = host->io_phys; + + if (nfc && nfc->write_by_sram) + dma_dst_addr = nfc_sram_phys(host); + else + dma_dst_addr = host->io_phys; } tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr, @@ -278,6 +421,10 @@ static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len, dma_async_issue_pending(host->dma_chan); wait_for_completion(&host->comp); + if (is_read && nfc && nfc->data_in_sram) + /* After read data from SRAM, need to increase the position */ + nfc->data_in_sram += len; + err = 0; err_dma: @@ -366,43 +513,34 @@ static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host) table_size * sizeof(int16_t); } -static void pmecc_data_free(struct atmel_nand_host *host) -{ - kfree(host->pmecc_partial_syn); - kfree(host->pmecc_si); - kfree(host->pmecc_lmu); - kfree(host->pmecc_smu); - kfree(host->pmecc_mu); - kfree(host->pmecc_dmu); - kfree(host->pmecc_delta); -} - static int pmecc_data_alloc(struct atmel_nand_host *host) { const int cap = host->pmecc_corr_cap; + int size; + + size = (2 * cap + 1) * sizeof(int16_t); + host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL); + host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL); + host->pmecc_lmu = devm_kzalloc(host->dev, + (cap + 1) * sizeof(int16_t), GFP_KERNEL); + host->pmecc_smu = devm_kzalloc(host->dev, + (cap + 2) * size, GFP_KERNEL); + + size = (cap + 1) * sizeof(int); + host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL); + host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL); + host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL); + + if (!host->pmecc_partial_syn || + !host->pmecc_si || + !host->pmecc_lmu || + !host->pmecc_smu || + !host->pmecc_mu || + !host->pmecc_dmu || + !host->pmecc_delta) + return -ENOMEM; - host->pmecc_partial_syn = kzalloc((2 * cap + 1) * sizeof(int16_t), - GFP_KERNEL); - host->pmecc_si = kzalloc((2 * cap + 1) * sizeof(int16_t), GFP_KERNEL); - host->pmecc_lmu = kzalloc((cap + 1) * sizeof(int16_t), GFP_KERNEL); - host->pmecc_smu = kzalloc((cap + 2) * (2 * cap + 1) * sizeof(int16_t), - GFP_KERNEL); - host->pmecc_mu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); - host->pmecc_dmu = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); - host->pmecc_delta = kzalloc((cap + 1) * sizeof(int), GFP_KERNEL); - - if (host->pmecc_partial_syn && - host->pmecc_si && - host->pmecc_lmu && - host->pmecc_smu && - host->pmecc_mu && - host->pmecc_dmu && - host->pmecc_delta) - return 0; - - /* error happened */ - pmecc_data_free(host); - return -ENOMEM; + return 0; } static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector) @@ -763,6 +901,30 @@ normal_check: return total_err; } +static void pmecc_enable(struct atmel_nand_host *host, int ecc_op) +{ + u32 val; + + if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) { + dev_err(host->dev, "atmel_nand: wrong pmecc operation type!"); + return; + } + + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); + val = pmecc_readl_relaxed(host->ecc, CFG); + + if (ecc_op == NAND_ECC_READ) + pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP) + | PMECC_CFG_AUTO_ENABLE); + else + pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP) + & ~PMECC_CFG_AUTO_ENABLE); + + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); + pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); +} + static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int oob_required, int page) { @@ -774,13 +936,8 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, unsigned long end_time; int bitflips = 0; - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); - pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) - & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE); - - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); + if (!host->nfc || !host->nfc->use_nfc_sram) + pmecc_enable(host, NAND_ECC_READ); chip->read_buf(mtd, buf, eccsize); chip->read_buf(mtd, oob, mtd->oobsize); @@ -813,16 +970,10 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, int i, j; unsigned long end_time; - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST); - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); - - pmecc_writel(host->ecc, CFG, (pmecc_readl_relaxed(host->ecc, CFG) | - PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE); - - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE); - pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA); - - chip->write_buf(mtd, (u8 *)buf, mtd->writesize); + if (!host->nfc || !host->nfc->write_by_sram) { + pmecc_enable(host, NAND_ECC_WRITE); + chip->write_buf(mtd, (u8 *)buf, mtd->writesize); + } end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS); while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) { @@ -967,11 +1118,11 @@ static int pmecc_choose_ecc(struct atmel_nand_host *host, host->pmecc_corr_cap = 2; else if (*cap <= 4) host->pmecc_corr_cap = 4; - else if (*cap < 8) + else if (*cap <= 8) host->pmecc_corr_cap = 8; - else if (*cap < 12) + else if (*cap <= 12) host->pmecc_corr_cap = 12; - else if (*cap < 24) + else if (*cap <= 24) host->pmecc_corr_cap = 24; else return -EINVAL; @@ -1002,7 +1153,7 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, return err_no; } - if (cap != host->pmecc_corr_cap || + if (cap > host->pmecc_corr_cap || sector_size != host->pmecc_sector_size) dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n"); @@ -1023,27 +1174,28 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, return 0; } - host->ecc = ioremap(regs->start, resource_size(regs)); - if (host->ecc == NULL) { + host->ecc = devm_ioremap_resource(&pdev->dev, regs); + if (IS_ERR(host->ecc)) { dev_err(host->dev, "ioremap failed\n"); - err_no = -EIO; - goto err_pmecc_ioremap; + err_no = PTR_ERR(host->ecc); + goto err; } regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2); - regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3); - if (regs_pmerr && regs_rom) { - host->pmerrloc_base = ioremap(regs_pmerr->start, - resource_size(regs_pmerr)); - host->pmecc_rom_base = ioremap(regs_rom->start, - resource_size(regs_rom)); + host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr); + if (IS_ERR(host->pmerrloc_base)) { + dev_err(host->dev, + "Can not get I/O resource for PMECC ERRLOC controller!\n"); + err_no = PTR_ERR(host->pmerrloc_base); + goto err; } - if (!host->pmerrloc_base || !host->pmecc_rom_base) { - dev_err(host->dev, - "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n"); - err_no = -EIO; - goto err_pmloc_ioremap; + regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3); + host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev, regs_rom); + if (IS_ERR(host->pmecc_rom_base)) { + dev_err(host->dev, "Can not get I/O resource for ROM!\n"); + err_no = PTR_ERR(host->pmecc_rom_base); + goto err; } /* ECC is calculated for the whole page (1 step) */ @@ -1052,7 +1204,8 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, /* set ECC page size and oob layout */ switch (mtd->writesize) { case 2048: - host->pmecc_degree = PMECC_GF_DIMENSION_13; + host->pmecc_degree = (sector_size == 512) ? + PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14; host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; host->pmecc_sector_number = mtd->writesize / sector_size; host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes( @@ -1068,7 +1221,7 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, if (nand_chip->ecc.bytes > mtd->oobsize - 2) { dev_err(host->dev, "No room for ECC bytes\n"); err_no = -EINVAL; - goto err_no_ecc_room; + goto err; } pmecc_config_ecc_layout(&atmel_pmecc_oobinfo, mtd->oobsize, @@ -1093,7 +1246,7 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, if (err_no) { dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n"); - goto err_pmecc_data_alloc; + goto err; } nand_chip->ecc.read_page = atmel_nand_pmecc_read_page; @@ -1103,15 +1256,7 @@ static int __init atmel_pmecc_nand_init_params(struct platform_device *pdev, return 0; -err_pmecc_data_alloc: -err_no_ecc_room: -err_pmloc_ioremap: - iounmap(host->ecc); - if (host->pmerrloc_base) - iounmap(host->pmerrloc_base); - if (host->pmecc_rom_base) - iounmap(host->pmecc_rom_base); -err_pmecc_ioremap: +err: return err_no; } @@ -1174,10 +1319,9 @@ static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, * Workaround: Reset the parity registers before reading the * actual data. */ - if (cpu_is_at32ap7000()) { - struct atmel_nand_host *host = chip->priv; + struct atmel_nand_host *host = chip->priv; + if (host->board.need_reset_workaround) ecc_writel(host->ecc, CR, ATMEL_ECC_RST); - } /* read the page */ chip->read_buf(mtd, p, eccsize); @@ -1298,11 +1442,11 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, */ static void atmel_nand_hwctl(struct mtd_info *mtd, int mode) { - if (cpu_is_at32ap7000()) { - struct nand_chip *nand_chip = mtd->priv; - struct atmel_nand_host *host = nand_chip->priv; + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + + if (host->board.need_reset_workaround) ecc_writel(host->ecc, CR, ATMEL_ECC_RST); - } } #if defined(CONFIG_OF) @@ -1337,6 +1481,8 @@ static int atmel_of_init_port(struct atmel_nand_host *host, board->on_flash_bbt = of_get_nand_on_flash_bbt(np); + board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma"); + if (of_get_nand_bus_width(np) == 16) board->bus_width_16 = 1; @@ -1348,6 +1494,9 @@ static int atmel_of_init_port(struct atmel_nand_host *host, host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc"); + /* load the nfc driver if there is */ + of_platform_populate(np, NULL, NULL, host->dev); + if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc) return 0; /* Not using PMECC */ @@ -1414,10 +1563,10 @@ static int __init atmel_hw_nand_init_params(struct platform_device *pdev, return 0; } - host->ecc = ioremap(regs->start, resource_size(regs)); - if (host->ecc == NULL) { + host->ecc = devm_ioremap_resource(&pdev->dev, regs); + if (IS_ERR(host->ecc)) { dev_err(host->dev, "ioremap failed\n"); - return -EIO; + return PTR_ERR(host->ecc); } /* ECC is calculated for the whole page (1 step) */ @@ -1459,6 +1608,382 @@ static int __init atmel_hw_nand_init_params(struct platform_device *pdev, return 0; } +/* SMC interrupt service routine */ +static irqreturn_t hsmc_interrupt(int irq, void *dev_id) +{ + struct atmel_nand_host *host = dev_id; + u32 status, mask, pending; + irqreturn_t ret = IRQ_HANDLED; + + status = nfc_readl(host->nfc->hsmc_regs, SR); + mask = nfc_readl(host->nfc->hsmc_regs, IMR); + pending = status & mask; + + if (pending & NFC_SR_XFR_DONE) { + complete(&host->nfc->comp_nfc); + nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE); + } else if (pending & NFC_SR_RB_EDGE) { + complete(&host->nfc->comp_nfc); + nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE); + } else if (pending & NFC_SR_CMD_DONE) { + complete(&host->nfc->comp_nfc); + nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE); + } else { + ret = IRQ_NONE; + } + + return ret; +} + +/* NFC(Nand Flash Controller) related functions */ +static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag) +{ + unsigned long timeout; + init_completion(&host->nfc->comp_nfc); + + /* Enable interrupt that need to wait for */ + nfc_writel(host->nfc->hsmc_regs, IER, flag); + + timeout = wait_for_completion_timeout(&host->nfc->comp_nfc, + msecs_to_jiffies(NFC_TIME_OUT_MS)); + if (timeout) + return 0; + + /* Time out to wait for the interrupt */ + dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag); + return -ETIMEDOUT; +} + +static int nfc_send_command(struct atmel_nand_host *host, + unsigned int cmd, unsigned int addr, unsigned char cycle0) +{ + unsigned long timeout; + dev_dbg(host->dev, + "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n", + cmd, addr, cycle0); + + timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS); + while (nfc_cmd_readl(NFCADDR_CMD_NFCBUSY, host->nfc->base_cmd_regs) + & NFCADDR_CMD_NFCBUSY) { + if (time_after(jiffies, timeout)) { + dev_err(host->dev, + "Time out to wait CMD_NFCBUSY ready!\n"); + return -ETIMEDOUT; + } + } + nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0); + nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs); + return nfc_wait_interrupt(host, NFC_SR_CMD_DONE); +} + +static int nfc_device_ready(struct mtd_info *mtd) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + if (!nfc_wait_interrupt(host, NFC_SR_RB_EDGE)) + return 1; + return 0; +} + +static void nfc_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *nand_chip = mtd->priv; + struct atmel_nand_host *host = nand_chip->priv; + + if (chip == -1) + nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE); + else + nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE); +} + +static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr, + unsigned int *addr1234, unsigned int *cycle0) +{ + struct nand_chip *chip = mtd->priv; + + int acycle = 0; + unsigned char addr_bytes[8]; + int index = 0, bit_shift; + + BUG_ON(addr1234 == NULL || cycle0 == NULL); + + *cycle0 = 0; + *addr1234 = 0; + + if (column != -1) { + if (chip->options & NAND_BUSWIDTH_16) + column >>= 1; + addr_bytes[acycle++] = column & 0xff; + if (mtd->writesize > 512) + addr_bytes[acycle++] = (column >> 8) & 0xff; + } + + if (page_addr != -1) { + addr_bytes[acycle++] = page_addr & 0xff; + addr_bytes[acycle++] = (page_addr >> 8) & 0xff; + if (chip->chipsize > (128 << 20)) + addr_bytes[acycle++] = (page_addr >> 16) & 0xff; + } + + if (acycle > 4) + *cycle0 = addr_bytes[index++]; + + for (bit_shift = 0; index < acycle; bit_shift += 8) + *addr1234 += addr_bytes[index++] << bit_shift; + + /* return acycle in cmd register */ + return acycle << NFCADDR_CMD_ACYCLE_BIT_POS; +} + +static void nfc_nand_command(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd->priv; + struct atmel_nand_host *host = chip->priv; + unsigned long timeout; + unsigned int nfc_addr_cmd = 0; + + unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS; + + /* Set default settings: no cmd2, no addr cycle. read from nand */ + unsigned int cmd2 = 0; + unsigned int vcmd2 = 0; + int acycle = NFCADDR_CMD_ACYCLE_NONE; + int csid = NFCADDR_CMD_CSID_3; + int dataen = NFCADDR_CMD_DATADIS; + int nfcwr = NFCADDR_CMD_NFCRD; + unsigned int addr1234 = 0; + unsigned int cycle0 = 0; + bool do_addr = true; + host->nfc->data_in_sram = NULL; + + dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n", + __func__, command, column, page_addr); + + switch (command) { + case NAND_CMD_RESET: + nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr; + nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0); + udelay(chip->chip_delay); + + nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1); + timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS); + while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) { + if (time_after(jiffies, timeout)) { + dev_err(host->dev, + "Time out to wait status ready!\n"); + break; + } + } + return; + case NAND_CMD_STATUS: + do_addr = false; + break; + case NAND_CMD_PARAM: + case NAND_CMD_READID: + do_addr = false; + acycle = NFCADDR_CMD_ACYCLE_1; + if (column != -1) + addr1234 = column; + break; + case NAND_CMD_RNDOUT: + cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS; + vcmd2 = NFCADDR_CMD_VCMD2; + break; + case NAND_CMD_READ0: + case NAND_CMD_READOOB: + if (command == NAND_CMD_READOOB) { + column += mtd->writesize; + command = NAND_CMD_READ0; /* only READ0 is valid */ + cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS; + } + if (host->nfc->use_nfc_sram) { + /* Enable Data transfer to sram */ + dataen = NFCADDR_CMD_DATAEN; + + /* Need enable PMECC now, since NFC will transfer + * data in bus after sending nfc read command. + */ + if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) + pmecc_enable(host, NAND_ECC_READ); + } + + cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS; + vcmd2 = NFCADDR_CMD_VCMD2; + break; + /* For prgramming command, the cmd need set to write enable */ + case NAND_CMD_PAGEPROG: + case NAND_CMD_SEQIN: + case NAND_CMD_RNDIN: + nfcwr = NFCADDR_CMD_NFCWR; + if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN) + dataen = NFCADDR_CMD_DATAEN; + break; + default: + break; + } + + if (do_addr) + acycle = nfc_make_addr(mtd, column, page_addr, &addr1234, + &cycle0); + + nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr; + nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0); + + if (dataen == NFCADDR_CMD_DATAEN) + if (nfc_wait_interrupt(host, NFC_SR_XFR_DONE)) + dev_err(host->dev, "something wrong, No XFR_DONE interrupt comes.\n"); + + /* + * Program and erase have their own busy handlers status, sequential + * in, and deplete1 need no delay. + */ + switch (command) { + case NAND_CMD_CACHEDPROG: + case NAND_CMD_PAGEPROG: + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: + case NAND_CMD_RNDIN: + case NAND_CMD_STATUS: + case NAND_CMD_RNDOUT: + case NAND_CMD_SEQIN: + case NAND_CMD_READID: + return; + + case NAND_CMD_READ0: + if (dataen == NFCADDR_CMD_DATAEN) { + host->nfc->data_in_sram = host->nfc->sram_bank0 + + nfc_get_sram_off(host); + return; + } + /* fall through */ + default: + nfc_wait_interrupt(host, NFC_SR_RB_EDGE); + } +} + +static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip, + uint32_t offset, int data_len, const uint8_t *buf, + int oob_required, int page, int cached, int raw) +{ + int cfg, len; + int status = 0; + struct atmel_nand_host *host = chip->priv; + void __iomem *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host); + + /* Subpage write is not supported */ + if (offset || (data_len < mtd->writesize)) + return -EINVAL; + + cfg = nfc_readl(host->nfc->hsmc_regs, CFG); + len = mtd->writesize; + + if (unlikely(raw)) { + len += mtd->oobsize; + nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE); + } else + nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE); + + /* Copy page data to sram that will write to nand via NFC */ + if (use_dma) { + if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0) + /* Fall back to use cpu copy */ + memcpy32_toio(sram, buf, len); + } else { + memcpy32_toio(sram, buf, len); + } + + if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) + /* + * When use NFC sram, need set up PMECC before send + * NAND_CMD_SEQIN command. Since when the nand command + * is sent, nfc will do transfer from sram and nand. + */ + pmecc_enable(host, NAND_ECC_WRITE); + + host->nfc->will_write_sram = true; + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + host->nfc->will_write_sram = false; + + if (likely(!raw)) + /* Need to write ecc into oob */ + status = chip->ecc.write_page(mtd, chip, buf, oob_required); + + if (status < 0) + return status; + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + if ((status & NAND_STATUS_FAIL) && (chip->errstat)) + status = chip->errstat(mtd, chip, FL_WRITING, status, page); + + if (status & NAND_STATUS_FAIL) + return -EIO; + + return 0; +} + +static int nfc_sram_init(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct atmel_nand_host *host = chip->priv; + int res = 0; + + /* Initialize the NFC CFG register */ + unsigned int cfg_nfc = 0; + + /* set page size and oob layout */ + switch (mtd->writesize) { + case 512: + cfg_nfc = NFC_CFG_PAGESIZE_512; + break; + case 1024: + cfg_nfc = NFC_CFG_PAGESIZE_1024; + break; + case 2048: + cfg_nfc = NFC_CFG_PAGESIZE_2048; + break; + case 4096: + cfg_nfc = NFC_CFG_PAGESIZE_4096; + break; + case 8192: + cfg_nfc = NFC_CFG_PAGESIZE_8192; + break; + default: + dev_err(host->dev, "Unsupported page size for NFC.\n"); + res = -ENXIO; + return res; + } + + /* oob bytes size = (NFCSPARESIZE + 1) * 4 + * Max support spare size is 512 bytes. */ + cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS + & NFC_CFG_NFC_SPARESIZE); + /* default set a max timeout */ + cfg_nfc |= NFC_CFG_RSPARE | + NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL; + + nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc); + + host->nfc->will_write_sram = false; + nfc_set_sram_bank(host, 0); + + /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */ + if (host->nfc->write_by_sram) { + if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) || + chip->ecc.mode == NAND_ECC_NONE) + chip->write_page = nfc_sram_write_page; + else + host->nfc->write_by_sram = false; + } + + dev_info(host->dev, "Using NFC Sram read %s\n", + host->nfc->write_by_sram ? "and write" : ""); + return 0; +} + +static struct platform_driver atmel_nand_nfc_driver; /* * Probe for the NAND device. */ @@ -1469,30 +1994,27 @@ static int __init atmel_nand_probe(struct platform_device *pdev) struct nand_chip *nand_chip; struct resource *mem; struct mtd_part_parser_data ppdata = {}; - int res; - struct pinctrl *pinctrl; - - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) { - printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n"); - return -ENXIO; - } + int res, irq; /* Allocate memory for the device structure (and zero it) */ - host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL); + host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); if (!host) { printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n"); return -ENOMEM; } - host->io_phys = (dma_addr_t)mem->start; + res = platform_driver_register(&atmel_nand_nfc_driver); + if (res) + dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n"); - host->io_base = ioremap(mem->start, resource_size(mem)); - if (host->io_base == NULL) { - printk(KERN_ERR "atmel_nand: ioremap failed\n"); - res = -EIO; + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + host->io_base = devm_ioremap_resource(&pdev->dev, mem); + if (IS_ERR(host->io_base)) { + dev_err(&pdev->dev, "atmel_nand: ioremap resource failed\n"); + res = PTR_ERR(host->io_base); goto err_nand_ioremap; } + host->io_phys = (dma_addr_t)mem->start; mtd = &host->mtd; nand_chip = &host->nand_chip; @@ -1500,9 +2022,9 @@ static int __init atmel_nand_probe(struct platform_device *pdev) if (pdev->dev.of_node) { res = atmel_of_init_port(host, pdev->dev.of_node); if (res) - goto err_ecc_ioremap; + goto err_nand_ioremap; } else { - memcpy(&host->board, pdev->dev.platform_data, + memcpy(&host->board, dev_get_platdata(&pdev->dev), sizeof(struct atmel_nand_data)); } @@ -1513,51 +2035,36 @@ static int __init atmel_nand_probe(struct platform_device *pdev) /* Set address of NAND IO lines */ nand_chip->IO_ADDR_R = host->io_base; nand_chip->IO_ADDR_W = host->io_base; - nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) { - dev_err(host->dev, "Failed to request pinctrl\n"); - res = PTR_ERR(pinctrl); - goto err_ecc_ioremap; - } + if (nand_nfc.is_initialized) { + /* NFC driver is probed and initialized */ + host->nfc = &nand_nfc; - if (gpio_is_valid(host->board.rdy_pin)) { - res = gpio_request(host->board.rdy_pin, "nand_rdy"); - if (res < 0) { - dev_err(&pdev->dev, - "can't request rdy gpio %d\n", - host->board.rdy_pin); - goto err_ecc_ioremap; - } + nand_chip->select_chip = nfc_select_chip; + nand_chip->dev_ready = nfc_device_ready; + nand_chip->cmdfunc = nfc_nand_command; - res = gpio_direction_input(host->board.rdy_pin); - if (res < 0) { - dev_err(&pdev->dev, - "can't request input direction rdy gpio %d\n", - host->board.rdy_pin); - goto err_ecc_ioremap; + /* Initialize the interrupt for NFC */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(host->dev, "Cannot get HSMC irq!\n"); + res = irq; + goto err_nand_ioremap; } - nand_chip->dev_ready = atmel_nand_device_ready; - } - - if (gpio_is_valid(host->board.enable_pin)) { - res = gpio_request(host->board.enable_pin, "nand_enable"); - if (res < 0) { - dev_err(&pdev->dev, - "can't request enable gpio %d\n", - host->board.enable_pin); - goto err_ecc_ioremap; + res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt, + 0, "hsmc", host); + if (res) { + dev_err(&pdev->dev, "Unable to request HSMC irq %d\n", + irq); + goto err_nand_ioremap; } + } else { + res = atmel_nand_set_enable_ready_pins(mtd); + if (res) + goto err_nand_ioremap; - res = gpio_direction_output(host->board.enable_pin, 1); - if (res < 0) { - dev_err(&pdev->dev, - "can't request output direction enable gpio %d\n", - host->board.enable_pin); - goto err_ecc_ioremap; - } + nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl; } nand_chip->ecc.mode = host->board.ecc_mode; @@ -1573,7 +2080,8 @@ static int __init atmel_nand_probe(struct platform_device *pdev) atmel_nand_enable(host); if (gpio_is_valid(host->board.det_pin)) { - res = gpio_request(host->board.det_pin, "nand_det"); + res = devm_gpio_request(&pdev->dev, + host->board.det_pin, "nand_det"); if (res < 0) { dev_err(&pdev->dev, "can't request det gpio %d\n", @@ -1601,7 +2109,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev) nand_chip->bbt_options |= NAND_BBT_USE_FLASH; } - if (!cpu_has_dma()) + if (!host->board.has_dma) use_dma = 0; if (use_dma) { @@ -1637,6 +2145,15 @@ static int __init atmel_nand_probe(struct platform_device *pdev) goto err_hw_ecc; } + /* initialize the nfc configuration register */ + if (host->nfc && host->nfc->use_nfc_sram) { + res = nfc_sram_init(mtd); + if (res) { + host->nfc->use_nfc_sram = false; + dev_err(host->dev, "Disable use nfc sram for data transfer.\n"); + } + } + /* second phase scan */ if (nand_scan_tail(mtd)) { res = -ENXIO; @@ -1651,27 +2168,16 @@ static int __init atmel_nand_probe(struct platform_device *pdev) return res; err_scan_tail: - if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) { + if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); - pmecc_data_free(host); - } - if (host->ecc) - iounmap(host->ecc); - if (host->pmerrloc_base) - iounmap(host->pmerrloc_base); - if (host->pmecc_rom_base) - iounmap(host->pmecc_rom_base); err_hw_ecc: err_scan_ident: err_no_card: atmel_nand_disable(host); - platform_set_drvdata(pdev, NULL); if (host->dma_chan) dma_release_channel(host->dma_chan); -err_ecc_ioremap: - iounmap(host->io_base); err_nand_ioremap: - kfree(host); + platform_driver_unregister(&atmel_nand_nfc_driver); return res; } @@ -1691,30 +2197,12 @@ static int __exit atmel_nand_remove(struct platform_device *pdev) pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE); pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE); - pmecc_data_free(host); } - if (gpio_is_valid(host->board.det_pin)) - gpio_free(host->board.det_pin); - - if (gpio_is_valid(host->board.enable_pin)) - gpio_free(host->board.enable_pin); - - if (gpio_is_valid(host->board.rdy_pin)) - gpio_free(host->board.rdy_pin); - - if (host->ecc) - iounmap(host->ecc); - if (host->pmecc_rom_base) - iounmap(host->pmecc_rom_base); - if (host->pmerrloc_base) - iounmap(host->pmerrloc_base); - if (host->dma_chan) dma_release_channel(host->dma_chan); - iounmap(host->io_base); - kfree(host); + platform_driver_unregister(&atmel_nand_nfc_driver); return 0; } @@ -1728,6 +2216,59 @@ static const struct of_device_id atmel_nand_dt_ids[] = { MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids); #endif +static int atmel_nand_nfc_probe(struct platform_device *pdev) +{ + struct atmel_nfc *nfc = &nand_nfc; + struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram; + + nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs); + if (IS_ERR(nfc->base_cmd_regs)) + return PTR_ERR(nfc->base_cmd_regs); + + nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); + nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs); + if (IS_ERR(nfc->hsmc_regs)) + return PTR_ERR(nfc->hsmc_regs); + + nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2); + if (nfc_sram) { + nfc->sram_bank0 = devm_ioremap_resource(&pdev->dev, nfc_sram); + if (IS_ERR(nfc->sram_bank0)) { + dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n", + PTR_ERR(nfc->sram_bank0)); + } else { + nfc->use_nfc_sram = true; + nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start; + + if (pdev->dev.of_node) + nfc->write_by_sram = of_property_read_bool( + pdev->dev.of_node, + "atmel,write-by-sram"); + } + } + + nfc->is_initialized = true; + dev_info(&pdev->dev, "NFC is probed.\n"); + return 0; +} + +#if defined(CONFIG_OF) +static struct of_device_id atmel_nand_nfc_match[] = { + { .compatible = "atmel,sama5d3-nfc" }, + { /* sentinel */ } +}; +#endif + +static struct platform_driver atmel_nand_nfc_driver = { + .driver = { + .name = "atmel_nand_nfc", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(atmel_nand_nfc_match), + }, + .probe = atmel_nand_nfc_probe, +}; + static struct platform_driver atmel_nand_driver = { .remove = __exit_p(atmel_nand_remove), .driver = { diff --git a/drivers/mtd/nand/atmel_nand_nfc.h b/drivers/mtd/nand/atmel_nand_nfc.h new file mode 100644 index 0000000..4efd117 --- /dev/null +++ b/drivers/mtd/nand/atmel_nand_nfc.h @@ -0,0 +1,98 @@ +/* + * Atmel Nand Flash Controller (NFC) - System peripherals regsters. + * Based on SAMA5D3 datasheet. + * + * © Copyright 2013 Atmel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef ATMEL_NAND_NFC_H +#define ATMEL_NAND_NFC_H + +/* + * HSMC NFC registers + */ +#define ATMEL_HSMC_NFC_CFG 0x00 /* NFC Configuration Register */ +#define NFC_CFG_PAGESIZE (7 << 0) +#define NFC_CFG_PAGESIZE_512 (0 << 0) +#define NFC_CFG_PAGESIZE_1024 (1 << 0) +#define NFC_CFG_PAGESIZE_2048 (2 << 0) +#define NFC_CFG_PAGESIZE_4096 (3 << 0) +#define NFC_CFG_PAGESIZE_8192 (4 << 0) +#define NFC_CFG_WSPARE (1 << 8) +#define NFC_CFG_RSPARE (1 << 9) +#define NFC_CFG_NFC_DTOCYC (0xf << 16) +#define NFC_CFG_NFC_DTOMUL (0x7 << 20) +#define NFC_CFG_NFC_SPARESIZE (0x7f << 24) +#define NFC_CFG_NFC_SPARESIZE_BIT_POS 24 + +#define ATMEL_HSMC_NFC_CTRL 0x04 /* NFC Control Register */ +#define NFC_CTRL_ENABLE (1 << 0) +#define NFC_CTRL_DISABLE (1 << 1) + +#define ATMEL_HSMC_NFC_SR 0x08 /* NFC Status Register */ +#define NFC_SR_XFR_DONE (1 << 16) +#define NFC_SR_CMD_DONE (1 << 17) +#define NFC_SR_RB_EDGE (1 << 24) + +#define ATMEL_HSMC_NFC_IER 0x0c +#define ATMEL_HSMC_NFC_IDR 0x10 +#define ATMEL_HSMC_NFC_IMR 0x14 +#define ATMEL_HSMC_NFC_CYCLE0 0x18 /* NFC Address Cycle Zero */ +#define ATMEL_HSMC_NFC_ADDR_CYCLE0 (0xff) + +#define ATMEL_HSMC_NFC_BANK 0x1c /* NFC Bank Register */ +#define ATMEL_HSMC_NFC_BANK0 (0 << 0) +#define ATMEL_HSMC_NFC_BANK1 (1 << 0) + +#define nfc_writel(addr, reg, value) \ + writel((value), (addr) + ATMEL_HSMC_NFC_##reg) + +#define nfc_readl(addr, reg) \ + readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg) + +/* + * NFC Address Command definitions + */ +#define NFCADDR_CMD_CMD1 (0xff << 2) /* Command for Cycle 1 */ +#define NFCADDR_CMD_CMD1_BIT_POS 2 +#define NFCADDR_CMD_CMD2 (0xff << 10) /* Command for Cycle 2 */ +#define NFCADDR_CMD_CMD2_BIT_POS 10 +#define NFCADDR_CMD_VCMD2 (0x1 << 18) /* Valid Cycle 2 Command */ +#define NFCADDR_CMD_ACYCLE (0x7 << 19) /* Number of Address required */ +#define NFCADDR_CMD_ACYCLE_NONE (0x0 << 19) +#define NFCADDR_CMD_ACYCLE_1 (0x1 << 19) +#define NFCADDR_CMD_ACYCLE_2 (0x2 << 19) +#define NFCADDR_CMD_ACYCLE_3 (0x3 << 19) +#define NFCADDR_CMD_ACYCLE_4 (0x4 << 19) +#define NFCADDR_CMD_ACYCLE_5 (0x5 << 19) +#define NFCADDR_CMD_ACYCLE_BIT_POS 19 +#define NFCADDR_CMD_CSID (0x7 << 22) /* Chip Select Identifier */ +#define NFCADDR_CMD_CSID_0 (0x0 << 22) +#define NFCADDR_CMD_CSID_1 (0x1 << 22) +#define NFCADDR_CMD_CSID_2 (0x2 << 22) +#define NFCADDR_CMD_CSID_3 (0x3 << 22) +#define NFCADDR_CMD_CSID_4 (0x4 << 22) +#define NFCADDR_CMD_CSID_5 (0x5 << 22) +#define NFCADDR_CMD_CSID_6 (0x6 << 22) +#define NFCADDR_CMD_CSID_7 (0x7 << 22) +#define NFCADDR_CMD_DATAEN (0x1 << 25) /* Data Transfer Enable */ +#define NFCADDR_CMD_DATADIS (0x0 << 25) /* Data Transfer Disable */ +#define NFCADDR_CMD_NFCRD (0x0 << 26) /* NFC Read Enable */ +#define NFCADDR_CMD_NFCWR (0x1 << 26) /* NFC Write Enable */ +#define NFCADDR_CMD_NFCBUSY (0x1 << 27) /* NFC Busy */ + +#define nfc_cmd_addr1234_writel(cmd, addr1234, nfc_base) \ + writel((addr1234), (cmd) + nfc_base) + +#define nfc_cmd_readl(bitstatus, nfc_base) \ + readl_relaxed((bitstatus) + nfc_base) + +#define NFC_TIME_OUT_MS 100 +#define NFC_SRAM_BANK1_OFFSET 0x1200 + +#endif diff --git a/drivers/mtd/nand/au1550nd.c b/drivers/mtd/nand/au1550nd.c index 217459d..ae8dd7c 100644 --- a/drivers/mtd/nand/au1550nd.c +++ b/drivers/mtd/nand/au1550nd.c @@ -411,7 +411,7 @@ static int au1550nd_probe(struct platform_device *pdev) struct resource *r; int ret, cs; - pd = pdev->dev.platform_data; + pd = dev_get_platdata(&pdev->dev); if (!pd) { dev_err(&pdev->dev, "missing platform data\n"); return -ENODEV; diff --git a/drivers/mtd/nand/bf5xx_nand.c b/drivers/mtd/nand/bf5xx_nand.c index 776df36..2c42e12 100644 --- a/drivers/mtd/nand/bf5xx_nand.c +++ b/drivers/mtd/nand/bf5xx_nand.c @@ -171,7 +171,7 @@ static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev) static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev) { - return pdev->dev.platform_data; + return dev_get_platdata(&pdev->dev); } /* @@ -671,8 +671,6 @@ static int bf5xx_nand_remove(struct platform_device *pdev) { struct bf5xx_nand_info *info = to_nand_info(pdev); - platform_set_drvdata(pdev, NULL); - /* first thing we need to do is release all our mtds * and their partitions, then go through freeing the * resources used @@ -832,7 +830,6 @@ static int bf5xx_nand_probe(struct platform_device *pdev) out_err_nand_scan: bf5xx_nand_dma_remove(info); out_err_hw_init: - platform_set_drvdata(pdev, NULL); kfree(info); out_err_kzalloc: peripheral_free_list(bfin_nfc_pin_req); diff --git a/drivers/mtd/nand/cs553x_nand.c b/drivers/mtd/nand/cs553x_nand.c index 2cdeab8..d469a9a 100644 --- a/drivers/mtd/nand/cs553x_nand.c +++ b/drivers/mtd/nand/cs553x_nand.c @@ -197,7 +197,7 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) } /* Allocate memory for MTD device structure and private data */ - new_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); + new_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL); if (!new_mtd) { printk(KERN_WARNING "Unable to allocate CS553X NAND MTD device structure.\n"); err = -ENOMEM; @@ -207,10 +207,6 @@ static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) /* Get pointer to private data */ this = (struct nand_chip *)(&new_mtd[1]); - /* Initialize structures */ - memset(new_mtd, 0, sizeof(struct mtd_info)); - memset(this, 0, sizeof(struct nand_chip)); - /* Link the private data with the MTD structure */ new_mtd->priv = this; new_mtd->owner = THIS_MODULE; diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index c3e15a5..b77a01e 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -530,7 +530,7 @@ MODULE_DEVICE_TABLE(of, davinci_nand_of_match); static struct davinci_nand_pdata *nand_davinci_get_pdata(struct platform_device *pdev) { - if (!pdev->dev.platform_data && pdev->dev.of_node) { + if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) { struct davinci_nand_pdata *pdata; const char *mode; u32 prop; @@ -575,13 +575,13 @@ static struct davinci_nand_pdata pdata->bbt_options = NAND_BBT_USE_FLASH; } - return pdev->dev.platform_data; + return dev_get_platdata(&pdev->dev); } #else static struct davinci_nand_pdata *nand_davinci_get_pdata(struct platform_device *pdev) { - return pdev->dev.platform_data; + return dev_get_platdata(&pdev->dev); } #endif @@ -623,11 +623,14 @@ static int __init nand_davinci_probe(struct platform_device *pdev) goto err_nomem; } - vaddr = devm_request_and_ioremap(&pdev->dev, res1); - base = devm_request_and_ioremap(&pdev->dev, res2); - if (!vaddr || !base) { - dev_err(&pdev->dev, "ioremap failed\n"); - ret = -EADDRNOTAVAIL; + vaddr = devm_ioremap_resource(&pdev->dev, res1); + if (IS_ERR(vaddr)) { + ret = PTR_ERR(vaddr); + goto err_ioremap; + } + base = devm_ioremap_resource(&pdev->dev, res2); + if (IS_ERR(base)) { + ret = PTR_ERR(base); goto err_ioremap; } diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 0c8bb6b..2ed2bb3 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1520,7 +1520,7 @@ int denali_init(struct denali_nand_info *denali) * so just let controller do 15bit ECC for MLC and 8bit ECC for * SLC if possible. * */ - if (denali->nand.cellinfo & 0xc && + if (denali->nand.cellinfo & NAND_CI_CELLTYPE_MSK && (denali->mtd.oobsize > (denali->bbtskipbytes + ECC_15BITS * (denali->mtd.writesize / ECC_SECTOR_SIZE)))) { diff --git a/drivers/mtd/nand/diskonchip.c b/drivers/mtd/nand/diskonchip.c index 81fa578..eaa3c29 100644 --- a/drivers/mtd/nand/diskonchip.c +++ b/drivers/mtd/nand/diskonchip.c @@ -46,13 +46,13 @@ static unsigned long __initdata doc_locations[] = { 0xfffd8000, 0xfffda000, 0xfffdc000, 0xfffde000, 0xfffe0000, 0xfffe2000, 0xfffe4000, 0xfffe6000, 0xfffe8000, 0xfffea000, 0xfffec000, 0xfffee000, -#else /* CONFIG_MTD_DOCPROBE_HIGH */ +#else 0xc8000, 0xca000, 0xcc000, 0xce000, 0xd0000, 0xd2000, 0xd4000, 0xd6000, 0xd8000, 0xda000, 0xdc000, 0xde000, 0xe0000, 0xe2000, 0xe4000, 0xe6000, 0xe8000, 0xea000, 0xec000, 0xee000, -#endif /* CONFIG_MTD_DOCPROBE_HIGH */ +#endif #endif 0xffffffff }; diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c index fa25e7a..548db23 100644 --- a/drivers/mtd/nand/docg4.c +++ b/drivers/mtd/nand/docg4.c @@ -1093,7 +1093,6 @@ static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs) struct nand_chip *nand = mtd->priv; struct docg4_priv *doc = nand->priv; struct nand_bbt_descr *bbtd = nand->badblock_pattern; - int block = (int)(ofs >> nand->bbt_erase_shift); int page = (int)(ofs >> nand->page_shift); uint32_t g4_addr = mtd_to_docg4_address(page, 0); @@ -1108,9 +1107,6 @@ static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs) if (buf == NULL) return -ENOMEM; - /* update bbt in memory */ - nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2); - /* write bit-wise negation of pattern to oob buffer */ memset(nand->oob_poi, 0xff, mtd->oobsize); for (i = 0; i < bbtd->len; i++) @@ -1120,8 +1116,6 @@ static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs) write_page_prologue(mtd, g4_addr); docg4_write_page(mtd, nand, buf, 1); ret = pageprog(mtd); - if (!ret) - mtd->ecc_stats.badblocks++; kfree(buf); @@ -1368,7 +1362,6 @@ static int __init probe_docg4(struct platform_device *pdev) struct nand_chip *nand = mtd->priv; struct docg4_priv *doc = nand->priv; nand_release(mtd); /* deletes partitions and mtd devices */ - platform_set_drvdata(pdev, NULL); free_bch(doc->bch); kfree(mtd); } @@ -1380,7 +1373,6 @@ static int __exit cleanup_docg4(struct platform_device *pdev) { struct docg4_priv *doc = platform_get_drvdata(pdev); nand_release(doc->mtd); - platform_set_drvdata(pdev, NULL); free_bch(doc->bch); kfree(doc->mtd); iounmap(doc->virtadr); diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index f1f7f12..317a771 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -823,7 +823,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) /* set up nand options */ chip->bbt_options = NAND_BBT_USE_FLASH; - + chip->options = NAND_NO_SUBPAGE_WRITE; if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) { chip->read_byte = fsl_ifc_read_byte16; @@ -908,7 +908,6 @@ static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv) ifc_nand_ctrl->chips[priv->bank] = NULL; dev_set_drvdata(priv->dev, NULL); - kfree(priv); return 0; } diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 911e243..3dc1a75 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -889,6 +889,24 @@ static int fsmc_nand_probe_config_dt(struct platform_device *pdev, if (of_get_property(np, "nand-skip-bbtscan", NULL)) pdata->options = NAND_SKIP_BBTSCAN; + pdata->nand_timings = devm_kzalloc(&pdev->dev, + sizeof(*pdata->nand_timings), GFP_KERNEL); + if (!pdata->nand_timings) { + dev_err(&pdev->dev, "no memory for nand_timing\n"); + return -ENOMEM; + } + of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings, + sizeof(*pdata->nand_timings)); + + /* Set default NAND bank to 0 */ + pdata->bank = 0; + if (!of_property_read_u32(np, "bank", &val)) { + if (val > 3) { + dev_err(&pdev->dev, "invalid bank %u\n", val); + return -EINVAL; + } + pdata->bank = val; + } return 0; } #else @@ -940,9 +958,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); - if (!res) - return -EINVAL; - host->data_va = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(host->data_va)) return PTR_ERR(host->data_va); @@ -950,25 +965,16 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) host->data_pa = (dma_addr_t)res->start; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); - if (!res) - return -EINVAL; - host->addr_va = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(host->addr_va)) return PTR_ERR(host->addr_va); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); - if (!res) - return -EINVAL; - host->cmd_va = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(host->cmd_va)) return PTR_ERR(host->cmd_va); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); - if (!res) - return -EINVAL; - host->regs_va = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(host->regs_va)) return PTR_ERR(host->regs_va); @@ -1174,8 +1180,6 @@ static int fsmc_nand_remove(struct platform_device *pdev) { struct fsmc_nand_data *host = platform_get_drvdata(pdev); - platform_set_drvdata(pdev, NULL); - if (host) { nand_release(&host->mtd); @@ -1190,7 +1194,7 @@ static int fsmc_nand_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int fsmc_nand_suspend(struct device *dev) { struct fsmc_nand_data *host = dev_get_drvdata(dev); @@ -1210,9 +1214,9 @@ static int fsmc_nand_resume(struct device *dev) } return 0; } +#endif static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); -#endif #ifdef CONFIG_OF static const struct of_device_id fsmc_nand_id_table[] = { @@ -1229,9 +1233,7 @@ static struct platform_driver fsmc_nand_driver = { .owner = THIS_MODULE, .name = "fsmc-nand", .of_match_table = of_match_ptr(fsmc_nand_id_table), -#ifdef CONFIG_PM .pm = &fsmc_nand_pm_ops, -#endif }, }; diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c index 89065dd..e826f89 100644 --- a/drivers/mtd/nand/gpio.c +++ b/drivers/mtd/nand/gpio.c @@ -17,6 +17,7 @@ */ #include <linux/kernel.h> +#include <linux/err.h> #include <linux/init.h> #include <linux/slab.h> #include <linux/module.h> @@ -86,59 +87,11 @@ static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) gpio_nand_dosync(gpiomtd); } -static void gpio_nand_writebuf(struct mtd_info *mtd, const u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - - iowrite8_rep(this->IO_ADDR_W, buf, len); -} - -static void gpio_nand_readbuf(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - - ioread8_rep(this->IO_ADDR_R, buf, len); -} - -static void gpio_nand_writebuf16(struct mtd_info *mtd, const u_char *buf, - int len) -{ - struct nand_chip *this = mtd->priv; - - if (IS_ALIGNED((unsigned long)buf, 2)) { - iowrite16_rep(this->IO_ADDR_W, buf, len>>1); - } else { - int i; - unsigned short *ptr = (unsigned short *)buf; - - for (i = 0; i < len; i += 2, ptr++) - writew(*ptr, this->IO_ADDR_W); - } -} - -static void gpio_nand_readbuf16(struct mtd_info *mtd, u_char *buf, int len) -{ - struct nand_chip *this = mtd->priv; - - if (IS_ALIGNED((unsigned long)buf, 2)) { - ioread16_rep(this->IO_ADDR_R, buf, len>>1); - } else { - int i; - unsigned short *ptr = (unsigned short *)buf; - - for (i = 0; i < len; i += 2, ptr++) - *ptr = readw(this->IO_ADDR_R); - } -} - static int gpio_nand_devready(struct mtd_info *mtd) { struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd); - if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) - return gpio_get_value(gpiomtd->plat.gpio_rdy); - - return 1; + return gpio_get_value(gpiomtd->plat.gpio_rdy); } #ifdef CONFIG_OF @@ -153,6 +106,9 @@ static int gpio_nand_get_config_of(const struct device *dev, { u32 val; + if (!dev->of_node) + return -ENODEV; + if (!of_property_read_u32(dev->of_node, "bank-width", &val)) { if (val == 2) { plat->options |= NAND_BUSWIDTH_16; @@ -211,8 +167,8 @@ static inline int gpio_nand_get_config(const struct device *dev, if (!ret) return ret; - if (dev->platform_data) { - memcpy(plat, dev->platform_data, sizeof(*plat)); + if (dev_get_platdata(dev)) { + memcpy(plat, dev_get_platdata(dev), sizeof(*plat)); return 0; } @@ -230,145 +186,100 @@ gpio_nand_get_io_sync(struct platform_device *pdev) return platform_get_resource(pdev, IORESOURCE_MEM, 1); } -static int gpio_nand_remove(struct platform_device *dev) +static int gpio_nand_remove(struct platform_device *pdev) { - struct gpiomtd *gpiomtd = platform_get_drvdata(dev); - struct resource *res; + struct gpiomtd *gpiomtd = platform_get_drvdata(pdev); nand_release(&gpiomtd->mtd_info); - res = gpio_nand_get_io_sync(dev); - iounmap(gpiomtd->io_sync); - if (res) - release_mem_region(res->start, resource_size(res)); - - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - iounmap(gpiomtd->nand_chip.IO_ADDR_R); - release_mem_region(res->start, resource_size(res)); - if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) gpio_set_value(gpiomtd->plat.gpio_nwp, 0); gpio_set_value(gpiomtd->plat.gpio_nce, 1); - gpio_free(gpiomtd->plat.gpio_cle); - gpio_free(gpiomtd->plat.gpio_ale); - gpio_free(gpiomtd->plat.gpio_nce); - if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) - gpio_free(gpiomtd->plat.gpio_nwp); - if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) - gpio_free(gpiomtd->plat.gpio_rdy); - return 0; } -static void __iomem *request_and_remap(struct resource *res, size_t size, - const char *name, int *err) -{ - void __iomem *ptr; - - if (!request_mem_region(res->start, resource_size(res), name)) { - *err = -EBUSY; - return NULL; - } - - ptr = ioremap(res->start, size); - if (!ptr) { - release_mem_region(res->start, resource_size(res)); - *err = -ENOMEM; - } - return ptr; -} - -static int gpio_nand_probe(struct platform_device *dev) +static int gpio_nand_probe(struct platform_device *pdev) { struct gpiomtd *gpiomtd; - struct nand_chip *this; - struct resource *res0, *res1; + struct nand_chip *chip; + struct resource *res; struct mtd_part_parser_data ppdata = {}; int ret = 0; - if (!dev->dev.of_node && !dev->dev.platform_data) - return -EINVAL; - - res0 = platform_get_resource(dev, IORESOURCE_MEM, 0); - if (!res0) + if (!pdev->dev.of_node && !dev_get_platdata(&pdev->dev)) return -EINVAL; - gpiomtd = devm_kzalloc(&dev->dev, sizeof(*gpiomtd), GFP_KERNEL); - if (gpiomtd == NULL) { - dev_err(&dev->dev, "failed to create NAND MTD\n"); + gpiomtd = devm_kzalloc(&pdev->dev, sizeof(*gpiomtd), GFP_KERNEL); + if (!gpiomtd) { + dev_err(&pdev->dev, "failed to create NAND MTD\n"); return -ENOMEM; } - this = &gpiomtd->nand_chip; - this->IO_ADDR_R = request_and_remap(res0, 2, "NAND", &ret); - if (!this->IO_ADDR_R) { - dev_err(&dev->dev, "unable to map NAND\n"); - goto err_map; - } + chip = &gpiomtd->nand_chip; - res1 = gpio_nand_get_io_sync(dev); - if (res1) { - gpiomtd->io_sync = request_and_remap(res1, 4, "NAND sync", &ret); - if (!gpiomtd->io_sync) { - dev_err(&dev->dev, "unable to map sync NAND\n"); - goto err_sync; - } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(chip->IO_ADDR_R)) + return PTR_ERR(chip->IO_ADDR_R); + + res = gpio_nand_get_io_sync(pdev); + if (res) { + gpiomtd->io_sync = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(gpiomtd->io_sync)) + return PTR_ERR(gpiomtd->io_sync); } - ret = gpio_nand_get_config(&dev->dev, &gpiomtd->plat); + ret = gpio_nand_get_config(&pdev->dev, &gpiomtd->plat); if (ret) - goto err_nce; + return ret; - ret = gpio_request(gpiomtd->plat.gpio_nce, "NAND NCE"); + ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nce, "NAND NCE"); if (ret) - goto err_nce; + return ret; gpio_direction_output(gpiomtd->plat.gpio_nce, 1); + if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) { - ret = gpio_request(gpiomtd->plat.gpio_nwp, "NAND NWP"); + ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_nwp, + "NAND NWP"); if (ret) - goto err_nwp; - gpio_direction_output(gpiomtd->plat.gpio_nwp, 1); + return ret; } - ret = gpio_request(gpiomtd->plat.gpio_ale, "NAND ALE"); + + ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_ale, "NAND ALE"); if (ret) - goto err_ale; + return ret; gpio_direction_output(gpiomtd->plat.gpio_ale, 0); - ret = gpio_request(gpiomtd->plat.gpio_cle, "NAND CLE"); + + ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_cle, "NAND CLE"); if (ret) - goto err_cle; + return ret; gpio_direction_output(gpiomtd->plat.gpio_cle, 0); + if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) { - ret = gpio_request(gpiomtd->plat.gpio_rdy, "NAND RDY"); + ret = devm_gpio_request(&pdev->dev, gpiomtd->plat.gpio_rdy, + "NAND RDY"); if (ret) - goto err_rdy; + return ret; gpio_direction_input(gpiomtd->plat.gpio_rdy); + chip->dev_ready = gpio_nand_devready; } + chip->IO_ADDR_W = chip->IO_ADDR_R; + chip->ecc.mode = NAND_ECC_SOFT; + chip->options = gpiomtd->plat.options; + chip->chip_delay = gpiomtd->plat.chip_delay; + chip->cmd_ctrl = gpio_nand_cmd_ctrl; - this->IO_ADDR_W = this->IO_ADDR_R; - this->ecc.mode = NAND_ECC_SOFT; - this->options = gpiomtd->plat.options; - this->chip_delay = gpiomtd->plat.chip_delay; - - /* install our routines */ - this->cmd_ctrl = gpio_nand_cmd_ctrl; - this->dev_ready = gpio_nand_devready; + gpiomtd->mtd_info.priv = chip; + gpiomtd->mtd_info.owner = THIS_MODULE; - if (this->options & NAND_BUSWIDTH_16) { - this->read_buf = gpio_nand_readbuf16; - this->write_buf = gpio_nand_writebuf16; - } else { - this->read_buf = gpio_nand_readbuf; - this->write_buf = gpio_nand_writebuf; - } + platform_set_drvdata(pdev, gpiomtd); - /* set the mtd private data for the nand driver */ - gpiomtd->mtd_info.priv = this; - gpiomtd->mtd_info.owner = THIS_MODULE; + if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) + gpio_direction_output(gpiomtd->plat.gpio_nwp, 1); if (nand_scan(&gpiomtd->mtd_info, 1)) { - dev_err(&dev->dev, "no nand chips found?\n"); ret = -ENXIO; goto err_wp; } @@ -377,38 +288,17 @@ static int gpio_nand_probe(struct platform_device *dev) gpiomtd->plat.adjust_parts(&gpiomtd->plat, gpiomtd->mtd_info.size); - ppdata.of_node = dev->dev.of_node; + ppdata.of_node = pdev->dev.of_node; ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata, gpiomtd->plat.parts, gpiomtd->plat.num_parts); - if (ret) - goto err_wp; - platform_set_drvdata(dev, gpiomtd); - - return 0; + if (!ret) + return 0; err_wp: if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) gpio_set_value(gpiomtd->plat.gpio_nwp, 0); - if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) - gpio_free(gpiomtd->plat.gpio_rdy); -err_rdy: - gpio_free(gpiomtd->plat.gpio_cle); -err_cle: - gpio_free(gpiomtd->plat.gpio_ale); -err_ale: - if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) - gpio_free(gpiomtd->plat.gpio_nwp); -err_nwp: - gpio_free(gpiomtd->plat.gpio_nce); -err_nce: - iounmap(gpiomtd->io_sync); - if (res1) - release_mem_region(res1->start, resource_size(res1)); -err_sync: - iounmap(gpiomtd->nand_chip.IO_ADDR_R); - release_mem_region(res0->start, resource_size(res0)); -err_map: + return ret; } @@ -417,6 +307,7 @@ static struct platform_driver gpio_nand_driver = { .remove = gpio_nand_remove, .driver = { .name = "gpio-nand", + .owner = THIS_MODULE, .of_match_table = of_match_ptr(gpio_nand_id_table), }, }; diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 25ecfa1..59ab069 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -26,7 +26,6 @@ #include <linux/interrupt.h> #include <linux/module.h> #include <linux/mtd/partitions.h> -#include <linux/pinctrl/consumer.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/of_mtd.h> @@ -112,7 +111,131 @@ static inline bool gpmi_check_ecc(struct gpmi_nand_data *this) return true; } -int common_nfc_set_geometry(struct gpmi_nand_data *this) +/* + * If we can get the ECC information from the nand chip, we do not + * need to calculate them ourselves. + * + * We may have available oob space in this case. + */ +static bool set_geometry_by_ecc_info(struct gpmi_nand_data *this) +{ + struct bch_geometry *geo = &this->bch_geometry; + struct mtd_info *mtd = &this->mtd; + struct nand_chip *chip = mtd->priv; + struct nand_oobfree *of = gpmi_hw_ecclayout.oobfree; + unsigned int block_mark_bit_offset; + + if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) + return false; + + switch (chip->ecc_step_ds) { + case SZ_512: + geo->gf_len = 13; + break; + case SZ_1K: + geo->gf_len = 14; + break; + default: + dev_err(this->dev, + "unsupported nand chip. ecc bits : %d, ecc size : %d\n", + chip->ecc_strength_ds, chip->ecc_step_ds); + return false; + } + geo->ecc_chunk_size = chip->ecc_step_ds; + geo->ecc_strength = round_up(chip->ecc_strength_ds, 2); + if (!gpmi_check_ecc(this)) + return false; + + /* Keep the C >= O */ + if (geo->ecc_chunk_size < mtd->oobsize) { + dev_err(this->dev, + "unsupported nand chip. ecc size: %d, oob size : %d\n", + chip->ecc_step_ds, mtd->oobsize); + return false; + } + + /* The default value, see comment in the legacy_set_geometry(). */ + geo->metadata_size = 10; + + geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size; + + /* + * Now, the NAND chip with 2K page(data chunk is 512byte) shows below: + * + * | P | + * |<----------------------------------------------------->| + * | | + * | (Block Mark) | + * | P' | | | | + * |<-------------------------------------------->| D | | O' | + * | |<---->| |<--->| + * V V V V V + * +---+----------+-+----------+-+----------+-+----------+-+-----+ + * | M | data |E| data |E| data |E| data |E| | + * +---+----------+-+----------+-+----------+-+----------+-+-----+ + * ^ ^ + * | O | + * |<------------>| + * | | + * + * P : the page size for BCH module. + * E : The ECC strength. + * G : the length of Galois Field. + * N : The chunk count of per page. + * M : the metasize of per page. + * C : the ecc chunk size, aka the "data" above. + * P': the nand chip's page size. + * O : the nand chip's oob size. + * O': the free oob. + * + * The formula for P is : + * + * E * G * N + * P = ------------ + P' + M + * 8 + * + * The position of block mark moves forward in the ECC-based view + * of page, and the delta is: + * + * E * G * (N - 1) + * D = (---------------- + M) + * 8 + * + * Please see the comment in legacy_set_geometry(). + * With the condition C >= O , we still can get same result. + * So the bit position of the physical block mark within the ECC-based + * view of the page is : + * (P' - D) * 8 + */ + geo->page_size = mtd->writesize + geo->metadata_size + + (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8; + + /* The available oob size we have. */ + if (geo->page_size < mtd->writesize + mtd->oobsize) { + of->offset = geo->page_size - mtd->writesize; + of->length = mtd->oobsize - of->offset; + } + + geo->payload_size = mtd->writesize; + + geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4); + geo->auxiliary_size = ALIGN(geo->metadata_size, 4) + + ALIGN(geo->ecc_chunk_count, 4); + + if (!this->swap_block_mark) + return true; + + /* For bit swap. */ + block_mark_bit_offset = mtd->writesize * 8 - + (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) + + geo->metadata_size * 8); + + geo->block_mark_byte_offset = block_mark_bit_offset / 8; + geo->block_mark_bit_offset = block_mark_bit_offset % 8; + return true; +} + +static int legacy_set_geometry(struct gpmi_nand_data *this) { struct bch_geometry *geo = &this->bch_geometry; struct mtd_info *mtd = &this->mtd; @@ -224,6 +347,11 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this) return 0; } +int common_nfc_set_geometry(struct gpmi_nand_data *this) +{ + return set_geometry_by_ecc_info(this) ? 0 : legacy_set_geometry(this); +} + struct dma_chan *get_dma_chan(struct gpmi_nand_data *this) { int chipnr = this->current_chip; @@ -355,7 +483,7 @@ static int acquire_register_block(struct gpmi_nand_data *this, r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name); if (!r) { pr_err("Can't get resource for %s\n", res_name); - return -ENXIO; + return -ENODEV; } p = ioremap(r->start, resource_size(r)); @@ -396,7 +524,7 @@ static int acquire_bch_irq(struct gpmi_nand_data *this, irq_handler_t irq_h) r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name); if (!r) { pr_err("Can't get resource for %s\n", res_name); - return -ENXIO; + return -ENODEV; } err = request_irq(r->start, irq_h, 0, res_name, this); @@ -473,12 +601,14 @@ static int gpmi_get_clks(struct gpmi_nand_data *this) struct resources *r = &this->resources; char **extra_clks = NULL; struct clk *clk; - int i; + int err, i; /* The main clock is stored in the first. */ r->clock[0] = clk_get(this->dev, "gpmi_io"); - if (IS_ERR(r->clock[0])) + if (IS_ERR(r->clock[0])) { + err = PTR_ERR(r->clock[0]); goto err_clock; + } /* Get extra clocks */ if (GPMI_IS_MX6Q(this)) @@ -491,8 +621,10 @@ static int gpmi_get_clks(struct gpmi_nand_data *this) break; clk = clk_get(this->dev, extra_clks[i - 1]); - if (IS_ERR(clk)) + if (IS_ERR(clk)) { + err = PTR_ERR(clk); goto err_clock; + } r->clock[i] = clk; } @@ -511,12 +643,11 @@ static int gpmi_get_clks(struct gpmi_nand_data *this) err_clock: dev_dbg(this->dev, "failed in finding the clocks.\n"); gpmi_put_clks(this); - return -ENOMEM; + return err; } static int acquire_resources(struct gpmi_nand_data *this) { - struct pinctrl *pinctrl; int ret; ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME); @@ -535,19 +666,12 @@ static int acquire_resources(struct gpmi_nand_data *this) if (ret) goto exit_dma_channels; - pinctrl = devm_pinctrl_get_select_default(&this->pdev->dev); - if (IS_ERR(pinctrl)) { - ret = PTR_ERR(pinctrl); - goto exit_pin; - } - ret = gpmi_get_clks(this); if (ret) goto exit_clock; return 0; exit_clock: -exit_pin: release_dma_channels(this); exit_dma_channels: release_bch_irq(this); @@ -1153,43 +1277,31 @@ static int gpmi_block_markbad(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd->priv; struct gpmi_nand_data *this = chip->priv; - int block, ret = 0; + int ret = 0; uint8_t *block_mark; int column, page, status, chipnr; - /* Get block number */ - block = (int)(ofs >> chip->bbt_erase_shift); - if (chip->bbt) - chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); + chipnr = (int)(ofs >> chip->chip_shift); + chip->select_chip(mtd, chipnr); - /* Do we have a flash based bad block table ? */ - if (chip->bbt_options & NAND_BBT_USE_FLASH) - ret = nand_update_bbt(mtd, ofs); - else { - chipnr = (int)(ofs >> chip->chip_shift); - chip->select_chip(mtd, chipnr); + column = this->swap_block_mark ? mtd->writesize : 0; - column = this->swap_block_mark ? mtd->writesize : 0; + /* Write the block mark. */ + block_mark = this->data_buffer_dma; + block_mark[0] = 0; /* bad block marker */ - /* Write the block mark. */ - block_mark = this->data_buffer_dma; - block_mark[0] = 0; /* bad block marker */ + /* Shift to get page */ + page = (int)(ofs >> chip->page_shift); - /* Shift to get page */ - page = (int)(ofs >> chip->page_shift); + chip->cmdfunc(mtd, NAND_CMD_SEQIN, column, page); + chip->write_buf(mtd, block_mark, 1); + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); - chip->cmdfunc(mtd, NAND_CMD_SEQIN, column, page); - chip->write_buf(mtd, block_mark, 1); - chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + if (status & NAND_STATUS_FAIL) + ret = -EIO; - status = chip->waitfunc(mtd, chip); - if (status & NAND_STATUS_FAIL) - ret = -EIO; - - chip->select_chip(mtd, -1); - } - if (!ret) - mtd->ecc_stats.badblocks++; + chip->select_chip(mtd, -1); return ret; } @@ -1469,19 +1581,22 @@ static int gpmi_pre_bbt_scan(struct gpmi_nand_data *this) if (ret) return ret; - /* Adjust the ECC strength according to the chip. */ - this->nand.ecc.strength = this->bch_geometry.ecc_strength; - this->mtd.ecc_strength = this->bch_geometry.ecc_strength; - this->mtd.bitflip_threshold = this->bch_geometry.ecc_strength; - /* NAND boot init, depends on the gpmi_set_geometry(). */ return nand_boot_init(this); } -static int gpmi_scan_bbt(struct mtd_info *mtd) +static void gpmi_nfc_exit(struct gpmi_nand_data *this) { + nand_release(&this->mtd); + gpmi_free_dma_buffer(this); +} + +static int gpmi_init_last(struct gpmi_nand_data *this) +{ + struct mtd_info *mtd = &this->mtd; struct nand_chip *chip = mtd->priv; - struct gpmi_nand_data *this = chip->priv; + struct nand_ecc_ctrl *ecc = &chip->ecc; + struct bch_geometry *bch_geo = &this->bch_geometry; int ret; /* Prepare for the BBT scan. */ @@ -1489,6 +1604,16 @@ static int gpmi_scan_bbt(struct mtd_info *mtd) if (ret) return ret; + /* Init the nand_ecc_ctrl{} */ + ecc->read_page = gpmi_ecc_read_page; + ecc->write_page = gpmi_ecc_write_page; + ecc->read_oob = gpmi_ecc_read_oob; + ecc->write_oob = gpmi_ecc_write_oob; + ecc->mode = NAND_ECC_HW; + ecc->size = bch_geo->ecc_chunk_size; + ecc->strength = bch_geo->ecc_strength; + ecc->layout = &gpmi_hw_ecclayout; + /* * Can we enable the extra features? such as EDO or Sync mode. * @@ -1497,14 +1622,7 @@ static int gpmi_scan_bbt(struct mtd_info *mtd) */ gpmi_extra_init(this); - /* use the default BBT implementation */ - return nand_default_bbt(mtd); -} - -static void gpmi_nfc_exit(struct gpmi_nand_data *this) -{ - nand_release(&this->mtd); - gpmi_free_dma_buffer(this); + return 0; } static int gpmi_nfc_init(struct gpmi_nand_data *this) @@ -1530,33 +1648,33 @@ static int gpmi_nfc_init(struct gpmi_nand_data *this) chip->read_byte = gpmi_read_byte; chip->read_buf = gpmi_read_buf; chip->write_buf = gpmi_write_buf; - chip->ecc.read_page = gpmi_ecc_read_page; - chip->ecc.write_page = gpmi_ecc_write_page; - chip->ecc.read_oob = gpmi_ecc_read_oob; - chip->ecc.write_oob = gpmi_ecc_write_oob; - chip->scan_bbt = gpmi_scan_bbt; chip->badblock_pattern = &gpmi_bbt_descr; chip->block_markbad = gpmi_block_markbad; chip->options |= NAND_NO_SUBPAGE_WRITE; - chip->ecc.mode = NAND_ECC_HW; - chip->ecc.size = 1; - chip->ecc.strength = 8; - chip->ecc.layout = &gpmi_hw_ecclayout; if (of_get_nand_on_flash_bbt(this->dev->of_node)) chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; - /* Allocate a temporary DMA buffer for reading ID in the nand_scan() */ + /* + * Allocate a temporary DMA buffer for reading ID in the + * nand_scan_ident(). + */ this->bch_geometry.payload_size = 1024; this->bch_geometry.auxiliary_size = 128; ret = gpmi_alloc_dma_buffer(this); if (ret) goto err_out; - ret = nand_scan(mtd, 1); - if (ret) { - pr_err("Chip scan failed\n"); + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) + goto err_out; + + ret = gpmi_init_last(this); + if (ret) + goto err_out; + + ret = nand_scan_tail(mtd); + if (ret) goto err_out; - } ppdata.of_node = this->pdev->dev.of_node; ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); @@ -1601,7 +1719,7 @@ static int gpmi_nand_probe(struct platform_device *pdev) pdev->id_entry = of_id->data; } else { pr_err("Failed to find the right device id.\n"); - return -ENOMEM; + return -ENODEV; } this = kzalloc(sizeof(*this), GFP_KERNEL); @@ -1633,7 +1751,6 @@ static int gpmi_nand_probe(struct platform_device *pdev) exit_nfc_init: release_resources(this); exit_acquire_resources: - platform_set_drvdata(pdev, NULL); dev_err(this->dev, "driver registration failed: %d\n", ret); kfree(this); @@ -1646,7 +1763,6 @@ static int gpmi_nand_remove(struct platform_device *pdev) gpmi_nfc_exit(this); release_resources(this); - platform_set_drvdata(pdev, NULL); kfree(this); return 0; } diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index b76460e..a264b88 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -411,7 +411,7 @@ static int jz_nand_probe(struct platform_device *pdev) struct jz_nand *nand; struct nand_chip *chip; struct mtd_info *mtd; - struct jz_nand_platform_data *pdata = pdev->dev.platform_data; + struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); size_t chipnr, bank_idx; uint8_t nand_maf_id = 0, nand_dev_id = 0; @@ -538,7 +538,6 @@ err_unclaim_banks: err_gpio_busy: if (pdata && gpio_is_valid(pdata->busy_gpio)) gpio_free(pdata->busy_gpio); - platform_set_drvdata(pdev, NULL); err_iounmap_mmio: jz_nand_iounmap_resource(nand->mem, nand->base); err_free: @@ -549,7 +548,7 @@ err_free: static int jz_nand_remove(struct platform_device *pdev) { struct jz_nand *nand = platform_get_drvdata(pdev); - struct jz_nand_platform_data *pdata = pdev->dev.platform_data; + struct jz_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); size_t i; nand_release(&nand->mtd); @@ -570,7 +569,6 @@ static int jz_nand_remove(struct platform_device *pdev) jz_nand_iounmap_resource(nand->mem, nand->base); - platform_set_drvdata(pdev, NULL); kfree(nand); return 0; diff --git a/drivers/mtd/nand/lpc32xx_mlc.c b/drivers/mtd/nand/lpc32xx_mlc.c index fd1df5e..f4dd2a8 100644 --- a/drivers/mtd/nand/lpc32xx_mlc.c +++ b/drivers/mtd/nand/lpc32xx_mlc.c @@ -696,7 +696,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) } lpc32xx_wp_disable(host); - host->pdata = pdev->dev.platform_data; + host->pdata = dev_get_platdata(&pdev->dev); nand_chip->priv = host; /* link the private data structures */ mtd->priv = nand_chip; @@ -828,7 +828,6 @@ err_exit3: err_exit2: clk_disable(host->clk); clk_put(host->clk); - platform_set_drvdata(pdev, NULL); err_exit1: lpc32xx_wp_enable(host); gpio_free(host->ncfg->wp_gpio); @@ -851,7 +850,6 @@ static int lpc32xx_nand_remove(struct platform_device *pdev) clk_disable(host->clk); clk_put(host->clk); - platform_set_drvdata(pdev, NULL); lpc32xx_wp_enable(host); gpio_free(host->ncfg->wp_gpio); diff --git a/drivers/mtd/nand/lpc32xx_slc.c b/drivers/mtd/nand/lpc32xx_slc.c index be94ed5..add7570 100644 --- a/drivers/mtd/nand/lpc32xx_slc.c +++ b/drivers/mtd/nand/lpc32xx_slc.c @@ -798,7 +798,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev) } lpc32xx_wp_disable(host); - host->pdata = pdev->dev.platform_data; + host->pdata = dev_get_platdata(&pdev->dev); mtd = &host->mtd; chip = &host->nand_chip; @@ -936,7 +936,6 @@ err_exit3: err_exit2: clk_disable(host->clk); clk_put(host->clk); - platform_set_drvdata(pdev, NULL); err_exit1: lpc32xx_wp_enable(host); gpio_free(host->ncfg->wp_gpio); @@ -963,7 +962,6 @@ static int lpc32xx_nand_remove(struct platform_device *pdev) clk_disable(host->clk); clk_put(host->clk); - platform_set_drvdata(pdev, NULL); lpc32xx_wp_enable(host); gpio_free(host->ncfg->wp_gpio); diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 07e5784..ce8242b 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -266,7 +266,7 @@ static struct nand_ecclayout nandv2_hw_eccoob_4k = { } }; -static const char const *part_probes[] = { +static const char * const part_probes[] = { "cmdlinepart", "RedBoot", "ofpart", NULL }; static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size) @@ -1432,7 +1432,8 @@ static int mxcnd_probe(struct platform_device *pdev) err = mxcnd_probe_dt(host); if (err > 0) { - struct mxc_nand_platform_data *pdata = pdev->dev.platform_data; + struct mxc_nand_platform_data *pdata = + dev_get_platdata(&pdev->dev); if (pdata) { host->pdata = *pdata; host->devtype_data = (struct mxc_nand_devtype_data *) @@ -1446,8 +1447,6 @@ static int mxcnd_probe(struct platform_device *pdev) if (host->devtype_data->needs_ip) { res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; host->regs_ip = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(host->regs_ip)) return PTR_ERR(host->regs_ip); @@ -1457,9 +1456,6 @@ static int mxcnd_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); } - if (!res) - return -ENODEV; - host->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(host->base)) return PTR_ERR(host->base); @@ -1578,8 +1574,6 @@ static int mxcnd_remove(struct platform_device *pdev) { struct mxc_nand_host *host = platform_get_drvdata(pdev); - platform_set_drvdata(pdev, NULL); - nand_release(&host->mtd); return 0; diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index dfcd0a5..7ed4841 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -108,13 +108,13 @@ static int check_offs_len(struct mtd_info *mtd, int ret = 0; /* Start address must align on block boundary */ - if (ofs & ((1 << chip->phys_erase_shift) - 1)) { + if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { pr_debug("%s: unaligned address\n", __func__); ret = -EINVAL; } /* Length must align on block boundary */ - if (len & ((1 << chip->phys_erase_shift) - 1)) { + if (len & ((1ULL << chip->phys_erase_shift) - 1)) { pr_debug("%s: length not block aligned\n", __func__); ret = -EINVAL; } @@ -211,11 +211,9 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr) */ static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { - int i; struct nand_chip *chip = mtd->priv; - for (i = 0; i < len; i++) - writeb(buf[i], chip->IO_ADDR_W); + iowrite8_rep(chip->IO_ADDR_W, buf, len); } /** @@ -228,11 +226,9 @@ static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) */ static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { - int i; struct nand_chip *chip = mtd->priv; - for (i = 0; i < len; i++) - buf[i] = readb(chip->IO_ADDR_R); + ioread8_rep(chip->IO_ADDR_R, buf, len); } /** @@ -245,14 +241,10 @@ static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) */ static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) { - int i; struct nand_chip *chip = mtd->priv; u16 *p = (u16 *) buf; - len >>= 1; - - for (i = 0; i < len; i++) - writew(p[i], chip->IO_ADDR_W); + iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); } /** @@ -265,13 +257,10 @@ static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) */ static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) { - int i; struct nand_chip *chip = mtd->priv; u16 *p = (u16 *) buf; - len >>= 1; - for (i = 0; i < len; i++) - p[i] = readw(chip->IO_ADDR_R); + ioread16_rep(chip->IO_ADDR_R, p, len >> 1); } /** @@ -335,80 +324,88 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) } /** - * nand_default_block_markbad - [DEFAULT] mark a block bad + * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker * @mtd: MTD device structure * @ofs: offset from device start * * This is the default implementation, which can be overridden by a hardware - * specific driver. We try operations in the following order, according to our - * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH): + * specific driver. It provides the details for writing a bad block marker to a + * block. + */ +static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +{ + struct nand_chip *chip = mtd->priv; + struct mtd_oob_ops ops; + uint8_t buf[2] = { 0, 0 }; + int ret = 0, res, i = 0; + + ops.datbuf = NULL; + ops.oobbuf = buf; + ops.ooboffs = chip->badblockpos; + if (chip->options & NAND_BUSWIDTH_16) { + ops.ooboffs &= ~0x01; + ops.len = ops.ooblen = 2; + } else { + ops.len = ops.ooblen = 1; + } + ops.mode = MTD_OPS_PLACE_OOB; + + /* Write to first/last page(s) if necessary */ + if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) + ofs += mtd->erasesize - mtd->writesize; + do { + res = nand_do_write_oob(mtd, ofs, &ops); + if (!ret) + ret = res; + + i++; + ofs += mtd->writesize; + } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); + + return ret; +} + +/** + * nand_block_markbad_lowlevel - mark a block bad + * @mtd: MTD device structure + * @ofs: offset from device start + * + * This function performs the generic NAND bad block marking steps (i.e., bad + * block table(s) and/or marker(s)). We only allow the hardware driver to + * specify how to write bad block markers to OOB (chip->block_markbad). + * + * We try operations in the following order: * (1) erase the affected block, to allow OOB marker to be written cleanly - * (2) update in-memory BBT - * (3) write bad block marker to OOB area of affected block - * (4) update flash-based BBT - * Note that we retain the first error encountered in (3) or (4), finish the + * (2) write bad block marker to OOB area of affected block (unless flag + * NAND_BBT_NO_OOB_BBM is present) + * (3) update the BBT + * Note that we retain the first error encountered in (2) or (3), finish the * procedures, and dump the error in the end. */ -static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) +static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) { struct nand_chip *chip = mtd->priv; - uint8_t buf[2] = { 0, 0 }; - int block, res, ret = 0, i = 0; - int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM); + int res, ret = 0; - if (write_oob) { + if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { struct erase_info einfo; /* Attempt erase before marking OOB */ memset(&einfo, 0, sizeof(einfo)); einfo.mtd = mtd; einfo.addr = ofs; - einfo.len = 1 << chip->phys_erase_shift; + einfo.len = 1ULL << chip->phys_erase_shift; nand_erase_nand(mtd, &einfo, 0); - } - - /* Get block number */ - block = (int)(ofs >> chip->bbt_erase_shift); - /* Mark block bad in memory-based BBT */ - if (chip->bbt) - chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); - - /* Write bad block marker to OOB */ - if (write_oob) { - struct mtd_oob_ops ops; - loff_t wr_ofs = ofs; + /* Write bad block marker to OOB */ nand_get_device(mtd, FL_WRITING); - - ops.datbuf = NULL; - ops.oobbuf = buf; - ops.ooboffs = chip->badblockpos; - if (chip->options & NAND_BUSWIDTH_16) { - ops.ooboffs &= ~0x01; - ops.len = ops.ooblen = 2; - } else { - ops.len = ops.ooblen = 1; - } - ops.mode = MTD_OPS_PLACE_OOB; - - /* Write to first/last page(s) if necessary */ - if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) - wr_ofs += mtd->erasesize - mtd->writesize; - do { - res = nand_do_write_oob(mtd, wr_ofs, &ops); - if (!ret) - ret = res; - - i++; - wr_ofs += mtd->writesize; - } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); - + ret = chip->block_markbad(mtd, ofs); nand_release_device(mtd); } - /* Update flash-based bad block table */ - if (chip->bbt_options & NAND_BBT_USE_FLASH) { - res = nand_update_bbt(mtd, ofs); + /* Mark block bad in BBT */ + if (chip->bbt) { + res = nand_markbad_bbt(mtd, ofs); if (!ret) ret = res; } @@ -1983,13 +1980,14 @@ static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write * @mtd: mtd info structure * @chip: nand chip info structure - * @column: column address of subpage within the page + * @offset: column address of subpage within the page * @data_len: data length + * @buf: data buffer * @oob_required: must write chip->oob_poi to OOB */ static int nand_write_subpage_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset, - uint32_t data_len, const uint8_t *data_buf, + uint32_t data_len, const uint8_t *buf, int oob_required) { uint8_t *oob_buf = chip->oob_poi; @@ -2008,20 +2006,20 @@ static int nand_write_subpage_hwecc(struct mtd_info *mtd, chip->ecc.hwctl(mtd, NAND_ECC_WRITE); /* write data (untouched subpages already masked by 0xFF) */ - chip->write_buf(mtd, data_buf, ecc_size); + chip->write_buf(mtd, buf, ecc_size); /* mask ECC of un-touched subpages by padding 0xFF */ if ((step < start_step) || (step > end_step)) memset(ecc_calc, 0xff, ecc_bytes); else - chip->ecc.calculate(mtd, data_buf, ecc_calc); + chip->ecc.calculate(mtd, buf, ecc_calc); /* mask OOB of un-touched subpages by padding 0xFF */ /* if oob_required, preserve OOB metadata of written subpage */ if (!oob_required || (step < start_step) || (step > end_step)) memset(oob_buf, 0xff, oob_bytes); - data_buf += ecc_size; + buf += ecc_size; ecc_calc += ecc_bytes; oob_buf += oob_bytes; } @@ -2633,7 +2631,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, } /* Increment page address and decrement length */ - len -= (1 << chip->phys_erase_shift); + len -= (1ULL << chip->phys_erase_shift); page += pages_per_block; /* Check, if we cross a chip boundary */ @@ -2694,7 +2692,6 @@ static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) */ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) { - struct nand_chip *chip = mtd->priv; int ret; ret = nand_block_isbad(mtd, ofs); @@ -2705,7 +2702,7 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) return ret; } - return chip->block_markbad(mtd, ofs); + return nand_block_markbad_lowlevel(mtd, ofs); } /** @@ -2720,7 +2717,9 @@ static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, { int status; - if (!chip->onfi_version) + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) return -EINVAL; chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1); @@ -2741,7 +2740,9 @@ static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, int addr, uint8_t *subfeature_param) { - if (!chip->onfi_version) + if (!chip->onfi_version || + !(le16_to_cpu(chip->onfi_params.opt_cmd) + & ONFI_OPT_CMD_SET_GET_FEATURES)) return -EINVAL; /* clear the sub feature parameters */ @@ -2793,7 +2794,15 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) if (!chip->select_chip) chip->select_chip = nand_select_chip; - if (!chip->read_byte) + + /* set for ONFI nand */ + if (!chip->onfi_set_features) + chip->onfi_set_features = nand_onfi_set_features; + if (!chip->onfi_get_features) + chip->onfi_get_features = nand_onfi_get_features; + + /* If called twice, pointers that depend on busw may need to be reset */ + if (!chip->read_byte || chip->read_byte == nand_read_byte) chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; if (!chip->read_word) chip->read_word = nand_read_word; @@ -2801,9 +2810,9 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->block_bad = nand_block_bad; if (!chip->block_markbad) chip->block_markbad = nand_default_block_markbad; - if (!chip->write_buf) + if (!chip->write_buf || chip->write_buf == nand_write_buf) chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; - if (!chip->read_buf) + if (!chip->read_buf || chip->read_buf == nand_read_buf) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; @@ -2846,6 +2855,78 @@ static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) return crc; } +/* Parse the Extended Parameter Page. */ +static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, + struct nand_chip *chip, struct nand_onfi_params *p) +{ + struct onfi_ext_param_page *ep; + struct onfi_ext_section *s; + struct onfi_ext_ecc_info *ecc; + uint8_t *cursor; + int ret = -EINVAL; + int len; + int i; + + len = le16_to_cpu(p->ext_param_page_length) * 16; + ep = kmalloc(len, GFP_KERNEL); + if (!ep) { + ret = -ENOMEM; + goto ext_out; + } + + /* Send our own NAND_CMD_PARAM. */ + chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1); + + /* Use the Change Read Column command to skip the ONFI param pages. */ + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, + sizeof(*p) * p->num_of_param_pages , -1); + + /* Read out the Extended Parameter Page. */ + chip->read_buf(mtd, (uint8_t *)ep, len); + if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) + != le16_to_cpu(ep->crc))) { + pr_debug("fail in the CRC.\n"); + goto ext_out; + } + + /* + * Check the signature. + * Do not strictly follow the ONFI spec, maybe changed in future. + */ + if (strncmp(ep->sig, "EPPS", 4)) { + pr_debug("The signature is invalid.\n"); + goto ext_out; + } + + /* find the ECC section. */ + cursor = (uint8_t *)(ep + 1); + for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { + s = ep->sections + i; + if (s->type == ONFI_SECTION_TYPE_2) + break; + cursor += s->length * 16; + } + if (i == ONFI_EXT_SECTION_MAX) { + pr_debug("We can not find the ECC section.\n"); + goto ext_out; + } + + /* get the info we want. */ + ecc = (struct onfi_ext_ecc_info *)cursor; + + if (ecc->codeword_size) { + chip->ecc_strength_ds = ecc->ecc_bits; + chip->ecc_step_ds = 1 << ecc->codeword_size; + } + + pr_info("ONFI extended param page detected.\n"); + return 0; + +ext_out: + kfree(ep); + return ret; +} + /* * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. */ @@ -2907,9 +2988,31 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); chip->chipsize = le32_to_cpu(p->blocks_per_lun); chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; - *busw = 0; - if (le16_to_cpu(p->features) & 1) + + if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) *busw = NAND_BUSWIDTH_16; + else + *busw = 0; + + if (p->ecc_bits != 0xff) { + chip->ecc_strength_ds = p->ecc_bits; + chip->ecc_step_ds = 512; + } else if (chip->onfi_version >= 21 && + (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { + + /* + * The nand_flash_detect_ext_param_page() uses the + * Change Read Column command which maybe not supported + * by the chip->cmdfunc. So try to update the chip->cmdfunc + * now. We do not replace user supplied command function. + */ + if (mtd->writesize > 512 && chip->cmdfunc == nand_command) + chip->cmdfunc = nand_command_lp; + + /* The Extended Parameter Page is supported since ONFI 2.1. */ + if (nand_flash_detect_ext_param_page(mtd, chip, p)) + pr_info("Failed to detect the extended param page.\n"); + } pr_info("ONFI flash detected\n"); return 1; @@ -3086,6 +3189,22 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip, extid >>= 2; /* Get buswidth information */ *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + + /* + * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per + * 512B page. For Toshiba SLC, we decode the 5th/6th byte as + * follows: + * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, + * 110b -> 24nm + * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC + */ + if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA && + !(chip->cellinfo & NAND_CI_CELLTYPE_MSK) && + (id_data[5] & 0x7) == 0x6 /* 24nm */ && + !(id_data[4] & 0x80) /* !BENAND */) { + mtd->oobsize = 32 * mtd->writesize >> 9; + } + } } @@ -3172,6 +3291,8 @@ static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, chip->cellinfo = id_data[2]; chip->chipsize = (uint64_t)type->chipsize << 20; chip->options |= type->options; + chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); + chip->ecc_step_ds = NAND_ECC_STEP(type); *busw = type->options & NAND_BUSWIDTH_16; @@ -3446,12 +3567,6 @@ int nand_scan_tail(struct mtd_info *mtd) if (!chip->write_page) chip->write_page = nand_write_page; - /* set for ONFI nand */ - if (!chip->onfi_set_features) - chip->onfi_set_features = nand_onfi_set_features; - if (!chip->onfi_get_features) - chip->onfi_get_features = nand_onfi_get_features; - /* * Check ECC mode, default to software if 3byte/512byte hardware ECC is * selected and we have 256 byte pagesize fallback to software ECC @@ -3674,6 +3789,7 @@ int nand_scan_tail(struct mtd_info *mtd) /* propagate ecc info to mtd_info */ mtd->ecclayout = chip->ecc.layout; mtd->ecc_strength = chip->ecc.strength; + mtd->ecc_step_size = chip->ecc.size; /* * Initialize bitflip_threshold to its default prior scan_bbt() call. * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 2672643..bc06196 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -71,6 +71,30 @@ #include <linux/export.h> #include <linux/string.h> +#define BBT_BLOCK_GOOD 0x00 +#define BBT_BLOCK_WORN 0x01 +#define BBT_BLOCK_RESERVED 0x02 +#define BBT_BLOCK_FACTORY_BAD 0x03 + +#define BBT_ENTRY_MASK 0x03 +#define BBT_ENTRY_SHIFT 2 + +static int nand_update_bbt(struct mtd_info *mtd, loff_t offs); + +static inline uint8_t bbt_get_entry(struct nand_chip *chip, int block) +{ + uint8_t entry = chip->bbt[block >> BBT_ENTRY_SHIFT]; + entry >>= (block & BBT_ENTRY_MASK) * 2; + return entry & BBT_ENTRY_MASK; +} + +static inline void bbt_mark_entry(struct nand_chip *chip, int block, + uint8_t mark) +{ + uint8_t msk = (mark & BBT_ENTRY_MASK) << ((block & BBT_ENTRY_MASK) * 2); + chip->bbt[block >> BBT_ENTRY_SHIFT] |= msk; +} + static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) { if (memcmp(buf, td->pattern, td->len)) @@ -86,33 +110,17 @@ static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td) * @td: search pattern descriptor * * Check for a pattern at the given place. Used to search bad block tables and - * good / bad block identifiers. If the SCAN_EMPTY option is set then check, if - * all bytes except the pattern area contain 0xff. + * good / bad block identifiers. */ static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td) { - int end = 0; - uint8_t *p = buf; - if (td->options & NAND_BBT_NO_OOB) return check_pattern_no_oob(buf, td); - end = paglen + td->offs; - if (td->options & NAND_BBT_SCANEMPTY) - if (memchr_inv(p, 0xff, end)) - return -1; - p += end; - /* Compare the pattern */ - if (memcmp(p, td->pattern, td->len)) + if (memcmp(buf + paglen + td->offs, td->pattern, td->len)) return -1; - if (td->options & NAND_BBT_SCANEMPTY) { - p += td->len; - end += td->len; - if (memchr_inv(p, 0xff, len - end)) - return -1; - } return 0; } @@ -159,7 +167,7 @@ static u32 add_marker_len(struct nand_bbt_descr *td) * @page: the starting page * @num: the number of bbt descriptors to read * @td: the bbt describtion table - * @offs: offset in the memory table + * @offs: block number offset in the table * * Read the bad block table starting from page. */ @@ -209,14 +217,16 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, /* Analyse data */ for (i = 0; i < len; i++) { uint8_t dat = buf[i]; - for (j = 0; j < 8; j += bits, act += 2) { + for (j = 0; j < 8; j += bits, act++) { uint8_t tmp = (dat >> j) & msk; if (tmp == msk) continue; if (reserved_block_code && (tmp == reserved_block_code)) { pr_info("nand_read_bbt: reserved block at 0x%012llx\n", - (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift); - this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); + (loff_t)(offs + act) << + this->bbt_erase_shift); + bbt_mark_entry(this, offs + act, + BBT_BLOCK_RESERVED); mtd->ecc_stats.bbtblocks++; continue; } @@ -225,12 +235,15 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, * move this message to pr_debug. */ pr_info("nand_read_bbt: bad block at 0x%012llx\n", - (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + (loff_t)(offs + act) << + this->bbt_erase_shift); /* Factory marked bad or worn out? */ if (tmp == 0) - this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); + bbt_mark_entry(this, offs + act, + BBT_BLOCK_FACTORY_BAD); else - this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06); + bbt_mark_entry(this, offs + act, + BBT_BLOCK_WORN); mtd->ecc_stats.badblocks++; } } @@ -265,7 +278,7 @@ static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc td, offs); if (res) return res; - offs += this->chipsize >> (this->bbt_erase_shift + 2); + offs += this->chipsize >> this->bbt_erase_shift; } } else { res = read_bbt(mtd, buf, td->pages[0], @@ -478,22 +491,12 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, else numpages = 1; - if (!(bd->options & NAND_BBT_SCANEMPTY)) { - /* We need only read few bytes from the OOB area */ - scanlen = 0; - readlen = bd->len; - } else { - /* Full page content should be read */ - scanlen = mtd->writesize + mtd->oobsize; - readlen = numpages * mtd->writesize; - } + /* We need only read few bytes from the OOB area */ + scanlen = 0; + readlen = bd->len; if (chip == -1) { - /* - * Note that numblocks is 2 * (real numblocks) here, see i+=2 - * below as it makes shifting and masking less painful - */ - numblocks = mtd->size >> (this->bbt_erase_shift - 1); + numblocks = mtd->size >> this->bbt_erase_shift; startblock = 0; from = 0; } else { @@ -502,16 +505,16 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, chip + 1, this->numchips); return -EINVAL; } - numblocks = this->chipsize >> (this->bbt_erase_shift - 1); + numblocks = this->chipsize >> this->bbt_erase_shift; startblock = chip * numblocks; numblocks += startblock; - from = (loff_t)startblock << (this->bbt_erase_shift - 1); + from = (loff_t)startblock << this->bbt_erase_shift; } if (this->bbt_options & NAND_BBT_SCANLASTPAGE) from += mtd->erasesize - (mtd->writesize * numpages); - for (i = startblock; i < numblocks;) { + for (i = startblock; i < numblocks; i++) { int ret; BUG_ON(bd->options & NAND_BBT_NO_OOB); @@ -526,13 +529,12 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, return ret; if (ret) { - this->bbt[i >> 3] |= 0x03 << (i & 0x6); + bbt_mark_entry(this, i, BBT_BLOCK_FACTORY_BAD); pr_warn("Bad eraseblock %d at 0x%012llx\n", - i >> 1, (unsigned long long)from); + i, (unsigned long long)from); mtd->ecc_stats.badblocks++; } - i += 2; from += (1 << this->bbt_erase_shift); } return 0; @@ -655,9 +657,9 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, { struct nand_chip *this = mtd->priv; struct erase_info einfo; - int i, j, res, chip = 0; + int i, res, chip = 0; int bits, startblock, dir, page, offs, numblocks, sft, sftmsk; - int nrchips, bbtoffs, pageoffs, ooboffs; + int nrchips, pageoffs, ooboffs; uint8_t msk[4]; uint8_t rcode = td->reserved_block_code; size_t retlen, len = 0; @@ -713,10 +715,9 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, for (i = 0; i < td->maxblocks; i++) { int block = startblock + dir * i; /* Check, if the block is bad */ - switch ((this->bbt[block >> 2] >> - (2 * (block & 0x03))) & 0x03) { - case 0x01: - case 0x03: + switch (bbt_get_entry(this, block)) { + case BBT_BLOCK_WORN: + case BBT_BLOCK_FACTORY_BAD: continue; } page = block << @@ -748,8 +749,6 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, default: return -EINVAL; } - bbtoffs = chip * (numblocks >> 2); - to = ((loff_t)page) << this->page_shift; /* Must we save the block contents? */ @@ -814,16 +813,12 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, buf[ooboffs + td->veroffs] = td->version[chip]; /* Walk through the memory table */ - for (i = 0; i < numblocks;) { + for (i = 0; i < numblocks; i++) { uint8_t dat; - dat = this->bbt[bbtoffs + (i >> 2)]; - for (j = 0; j < 4; j++, i++) { - int sftcnt = (i << (3 - sft)) & sftmsk; - /* Do not store the reserved bbt blocks! */ - buf[offs + (i >> sft)] &= - ~(msk[dat & 0x03] << sftcnt); - dat >>= 2; - } + int sftcnt = (i << (3 - sft)) & sftmsk; + dat = bbt_get_entry(this, chip * numblocks + i); + /* Do not store the reserved bbt blocks! */ + buf[offs + (i >> sft)] &= ~(msk[dat] << sftcnt); } memset(&einfo, 0, sizeof(einfo)); @@ -865,7 +860,6 @@ static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *b { struct nand_chip *this = mtd->priv; - bd->options &= ~NAND_BBT_SCANEMPTY; return create_bbt(mtd, this->buffers->databuf, bd, -1); } @@ -1009,7 +1003,7 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) { struct nand_chip *this = mtd->priv; int i, j, chips, block, nrblocks, update; - uint8_t oldval, newval; + uint8_t oldval; /* Do we have a bbt per chip? */ if (td->options & NAND_BBT_PERCHIP) { @@ -1026,12 +1020,12 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) if (td->pages[i] == -1) continue; block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift); - block <<= 1; - oldval = this->bbt[(block >> 3)]; - newval = oldval | (0x2 << (block & 0x06)); - this->bbt[(block >> 3)] = newval; - if ((oldval != newval) && td->reserved_block_code) - nand_update_bbt(mtd, (loff_t)block << (this->bbt_erase_shift - 1)); + oldval = bbt_get_entry(this, block); + bbt_mark_entry(this, block, BBT_BLOCK_RESERVED); + if ((oldval != BBT_BLOCK_RESERVED) && + td->reserved_block_code) + nand_update_bbt(mtd, (loff_t)block << + this->bbt_erase_shift); continue; } update = 0; @@ -1039,14 +1033,12 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) block = ((i + 1) * nrblocks) - td->maxblocks; else block = i * nrblocks; - block <<= 1; for (j = 0; j < td->maxblocks; j++) { - oldval = this->bbt[(block >> 3)]; - newval = oldval | (0x2 << (block & 0x06)); - this->bbt[(block >> 3)] = newval; - if (oldval != newval) + oldval = bbt_get_entry(this, block); + bbt_mark_entry(this, block, BBT_BLOCK_RESERVED); + if (oldval != BBT_BLOCK_RESERVED) update = 1; - block += 2; + block++; } /* * If we want reserved blocks to be recorded to flash, and some @@ -1054,7 +1046,8 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) * bbts. This should only happen once. */ if (update && td->reserved_block_code) - nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1)); + nand_update_bbt(mtd, (loff_t)(block - 1) << + this->bbt_erase_shift); } } @@ -1180,13 +1173,13 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) } /** - * nand_update_bbt - [NAND Interface] update bad block table(s) + * nand_update_bbt - update bad block table(s) * @mtd: MTD device structure * @offs: the offset of the newly marked block * * The function updates the bad block table(s). */ -int nand_update_bbt(struct mtd_info *mtd, loff_t offs) +static int nand_update_bbt(struct mtd_info *mtd, loff_t offs) { struct nand_chip *this = mtd->priv; int len, res = 0; @@ -1356,28 +1349,47 @@ int nand_default_bbt(struct mtd_info *mtd) int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) { struct nand_chip *this = mtd->priv; - int block; - uint8_t res; + int block, res; - /* Get block number * 2 */ - block = (int)(offs >> (this->bbt_erase_shift - 1)); - res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03; + block = (int)(offs >> this->bbt_erase_shift); + res = bbt_get_entry(this, block); pr_debug("nand_isbad_bbt(): bbt info for offs 0x%08x: " "(block %d) 0x%02x\n", - (unsigned int)offs, block >> 1, res); + (unsigned int)offs, block, res); - switch ((int)res) { - case 0x00: + switch (res) { + case BBT_BLOCK_GOOD: return 0; - case 0x01: + case BBT_BLOCK_WORN: return 1; - case 0x02: + case BBT_BLOCK_RESERVED: return allowbbt ? 0 : 1; } return 1; } +/** + * nand_markbad_bbt - [NAND Interface] Mark a block bad in the BBT + * @mtd: MTD device structure + * @offs: offset of the bad block + */ +int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs) +{ + struct nand_chip *this = mtd->priv; + int block, ret = 0; + + block = (int)(offs >> this->bbt_erase_shift); + + /* Mark bad block in memory */ + bbt_mark_entry(this, block, BBT_BLOCK_WORN); + + /* Update flash-based bad block table */ + if (this->bbt_options & NAND_BBT_USE_FLASH) + ret = nand_update_bbt(mtd, offs); + + return ret; +} + EXPORT_SYMBOL(nand_scan_bbt); EXPORT_SYMBOL(nand_default_bbt); -EXPORT_SYMBOL_GPL(nand_update_bbt); diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 683813a..a87b0a3 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -33,16 +33,16 @@ struct nand_flash_dev nand_flash_ids[] = { */ {"TC58NVG2S0F 4G 3.3V 8-bit", { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} }, - SZ_4K, SZ_512, SZ_256K, 0, 8, 224}, + SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) }, {"TC58NVG3S0F 8G 3.3V 8-bit", { .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} }, - SZ_4K, SZ_1K, SZ_256K, 0, 8, 232}, + SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) }, {"TC58NVG5D2 32G 3.3V 8-bit", { .id = {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} }, - SZ_8K, SZ_4K, SZ_1M, 0, 8, 640}, + SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, {"TC58NVG6D2 64G 3.3V 8-bit", { .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} }, - SZ_8K, SZ_8K, SZ_2M, 0, 8, 640}, + SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c index cb38f3d..bdc1d15 100644 --- a/drivers/mtd/nand/nandsim.c +++ b/drivers/mtd/nand/nandsim.c @@ -205,7 +205,7 @@ MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should " /* Calculate the page offset in flash RAM image by (row, column) address */ #define NS_RAW_OFFSET(ns) \ - (((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column) + (((ns)->regs.row * (ns)->geom.pgszoob) + (ns)->regs.column) /* Calculate the OOB offset in flash RAM image by (row, column) address */ #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz) @@ -336,7 +336,6 @@ struct nandsim { uint pgsec; /* number of pages per sector */ uint secshift; /* bits number in sector size */ uint pgshift; /* bits number in page size */ - uint oobshift; /* bits number in OOB size */ uint pgaddrbytes; /* bytes per page address */ uint secaddrbytes; /* bytes per sector address */ uint idbytes; /* the number ID bytes that this chip outputs */ @@ -363,7 +362,7 @@ struct nandsim { /* Fields needed when using a cache file */ struct file *cfile; /* Open file */ - unsigned char *pages_written; /* Which pages have been written */ + unsigned long *pages_written; /* Which pages have been written */ void *file_buf; struct page *held_pages[NS_MAX_HELD_PAGES]; int held_cnt; @@ -586,7 +585,8 @@ static int alloc_device(struct nandsim *ns) err = -EINVAL; goto err_close; } - ns->pages_written = vzalloc(ns->geom.pgnum); + ns->pages_written = vzalloc(BITS_TO_LONGS(ns->geom.pgnum) * + sizeof(unsigned long)); if (!ns->pages_written) { NS_ERR("alloc_device: unable to allocate pages written array\n"); err = -ENOMEM; @@ -653,9 +653,7 @@ static void free_device(struct nandsim *ns) static char *get_partition_name(int i) { - char buf[64]; - sprintf(buf, "NAND simulator partition %d", i); - return kstrdup(buf, GFP_KERNEL); + return kasprintf(GFP_KERNEL, "NAND simulator partition %d", i); } /* @@ -690,7 +688,6 @@ static int init_nandsim(struct mtd_info *mtd) ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz; ns->geom.secshift = ffs(ns->geom.secsz) - 1; ns->geom.pgshift = chip->page_shift; - ns->geom.oobshift = ffs(ns->geom.oobsz) - 1; ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz; ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec; ns->options = 0; @@ -761,12 +758,6 @@ static int init_nandsim(struct mtd_info *mtd) ns->nbparts += 1; } - /* Detect how many ID bytes the NAND chip outputs */ - for (i = 0; nand_flash_ids[i].name != NULL; i++) { - if (second_id_byte != nand_flash_ids[i].dev_id) - continue; - } - if (ns->busw == 16) NS_WARN("16-bit flashes support wasn't tested\n"); @@ -780,7 +771,7 @@ static int init_nandsim(struct mtd_info *mtd) printk("bus width: %u\n", ns->busw); printk("bits in sector size: %u\n", ns->geom.secshift); printk("bits in page size: %u\n", ns->geom.pgshift); - printk("bits in OOB size: %u\n", ns->geom.oobshift); + printk("bits in OOB size: %u\n", ffs(ns->geom.oobsz) - 1); printk("flash size with OOB: %llu KiB\n", (unsigned long long)ns->geom.totszoob >> 10); printk("page address bytes: %u\n", ns->geom.pgaddrbytes); @@ -1442,7 +1433,7 @@ static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns) return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off; } -int do_read_error(struct nandsim *ns, int num) +static int do_read_error(struct nandsim *ns, int num) { unsigned int page_no = ns->regs.row; @@ -1454,7 +1445,7 @@ int do_read_error(struct nandsim *ns, int num) return 0; } -void do_bit_flips(struct nandsim *ns, int num) +static void do_bit_flips(struct nandsim *ns, int num) { if (bitflips && prandom_u32() < (1 << 22)) { int flips = 1; @@ -1479,7 +1470,7 @@ static void read_page(struct nandsim *ns, int num) union ns_mem *mypage; if (ns->cfile) { - if (!ns->pages_written[ns->regs.row]) { + if (!test_bit(ns->regs.row, ns->pages_written)) { NS_DBG("read_page: page %d not written\n", ns->regs.row); memset(ns->buf.byte, 0xFF, num); } else { @@ -1490,7 +1481,7 @@ static void read_page(struct nandsim *ns, int num) ns->regs.row, ns->regs.column + ns->regs.off); if (do_read_error(ns, num)) return; - pos = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off; + pos = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off; tx = read_file(ns, ns->cfile, ns->buf.byte, num, pos); if (tx != num) { NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx); @@ -1525,9 +1516,9 @@ static void erase_sector(struct nandsim *ns) if (ns->cfile) { for (i = 0; i < ns->geom.pgsec; i++) - if (ns->pages_written[ns->regs.row + i]) { + if (__test_and_clear_bit(ns->regs.row + i, + ns->pages_written)) { NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i); - ns->pages_written[ns->regs.row + i] = 0; } return; } @@ -1559,8 +1550,8 @@ static int prog_page(struct nandsim *ns, int num) NS_DBG("prog_page: writing page %d\n", ns->regs.row); pg_off = ns->file_buf + ns->regs.column + ns->regs.off; - off = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off; - if (!ns->pages_written[ns->regs.row]) { + off = (loff_t)NS_RAW_OFFSET(ns) + ns->regs.off; + if (!test_bit(ns->regs.row, ns->pages_written)) { all = 1; memset(ns->file_buf, 0xff, ns->geom.pgszoob); } else { @@ -1580,7 +1571,7 @@ static int prog_page(struct nandsim *ns, int num) NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx); return -1; } - ns->pages_written[ns->regs.row] = 1; + __set_bit(ns->regs.row, ns->pages_written); } else { tx = write_file(ns, ns->cfile, pg_off, num, off); if (tx != num) { diff --git a/drivers/mtd/nand/nuc900_nand.c b/drivers/mtd/nand/nuc900_nand.c index cd6be2e..5211515 100644 --- a/drivers/mtd/nand/nuc900_nand.c +++ b/drivers/mtd/nand/nuc900_nand.c @@ -324,8 +324,6 @@ static int nuc900_nand_remove(struct platform_device *pdev) kfree(nuc900_nand); - platform_set_drvdata(pdev, NULL); - return 0; } diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 81b80af..4ecf0e5 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -154,7 +154,7 @@ static struct nand_ecclayout omap_oobinfo; */ static uint8_t scan_ff_pattern[] = { 0xff }; static struct nand_bbt_descr bb_descrip_flashbased = { - .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, + .options = NAND_BBT_SCANALLPAGES, .offs = 0, .len = 1, .pattern = scan_ff_pattern, @@ -1831,7 +1831,7 @@ static int omap_nand_probe(struct platform_device *pdev) struct resource *res; struct mtd_part_parser_data ppdata = {}; - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); if (pdata == NULL) { dev_err(&pdev->dev, "platform data missing\n"); return -ENODEV; @@ -2087,7 +2087,6 @@ static int omap_nand_remove(struct platform_device *pdev) mtd); omap3_free_bch(&info->mtd); - platform_set_drvdata(pdev, NULL); if (info->dma) dma_release_channel(info->dma); diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index 8fbd002..a393a5b 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c @@ -130,8 +130,9 @@ static int __init orion_nand_probe(struct platform_device *pdev) if (!of_property_read_u32(pdev->dev.of_node, "chip-delay", &val)) board->chip_delay = (u8)val; - } else - board = pdev->dev.platform_data; + } else { + board = dev_get_platdata(&pdev->dev); + } mtd->priv = nc; mtd->owner = THIS_MODULE; @@ -186,7 +187,6 @@ no_dev: clk_disable_unprepare(clk); clk_put(clk); } - platform_set_drvdata(pdev, NULL); iounmap(io_base); no_res: kfree(nc); diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c index c004566..cad4cdc 100644 --- a/drivers/mtd/nand/plat_nand.c +++ b/drivers/mtd/nand/plat_nand.c @@ -30,7 +30,7 @@ static const char *part_probe_types[] = { "cmdlinepart", NULL }; */ static int plat_nand_probe(struct platform_device *pdev) { - struct platform_nand_data *pdata = pdev->dev.platform_data; + struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); struct mtd_part_parser_data ppdata; struct plat_nand_data *data; struct resource *res; @@ -122,7 +122,6 @@ static int plat_nand_probe(struct platform_device *pdev) out: if (pdata->ctrl.remove) pdata->ctrl.remove(pdev); - platform_set_drvdata(pdev, NULL); iounmap(data->io_base); out_release_io: release_mem_region(res->start, resource_size(res)); @@ -137,7 +136,7 @@ out_free: static int plat_nand_remove(struct platform_device *pdev) { struct plat_nand_data *data = platform_get_drvdata(pdev); - struct platform_nand_data *pdata = pdev->dev.platform_data; + struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev); struct resource *res; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index dec80ca..5db900d 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -25,7 +25,14 @@ #include <linux/of.h> #include <linux/of_device.h> +#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP) +#define ARCH_HAS_DMA +#endif + +#ifdef ARCH_HAS_DMA #include <mach/dma.h> +#endif + #include <linux/platform_data/mtd-nand-pxa3xx.h> #define CHIP_DELAY_TIMEOUT (2 * HZ/10) @@ -80,6 +87,7 @@ #define NDSR_RDDREQ (0x1 << 1) #define NDSR_WRCMDREQ (0x1) +#define NDCB0_LEN_OVRD (0x1 << 28) #define NDCB0_ST_ROW_EN (0x1 << 26) #define NDCB0_AUTO_RS (0x1 << 25) #define NDCB0_CSEL (0x1 << 24) @@ -123,9 +131,13 @@ enum { STATE_READY, }; +enum pxa3xx_nand_variant { + PXA3XX_NAND_VARIANT_PXA, + PXA3XX_NAND_VARIANT_ARMADA370, +}; + struct pxa3xx_nand_host { struct nand_chip chip; - struct pxa3xx_nand_cmdset *cmdset; struct mtd_info *mtd; void *info_data; @@ -139,10 +151,6 @@ struct pxa3xx_nand_host { unsigned int row_addr_cycles; size_t read_id_bytes; - /* cached register value */ - uint32_t reg_ndcr; - uint32_t ndtr0cs0; - uint32_t ndtr1cs0; }; struct pxa3xx_nand_info { @@ -171,9 +179,16 @@ struct pxa3xx_nand_info { struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; unsigned int state; + /* + * This driver supports NFCv1 (as found in PXA SoC) + * and NFCv2 (as found in Armada 370/XP SoC). + */ + enum pxa3xx_nand_variant variant; + int cs; int use_ecc; /* use HW ECC ? */ int use_dma; /* use DMA ? */ + int use_spare; /* use spare ? */ int is_ready; unsigned int page_size; /* page size of attached chip */ @@ -181,33 +196,22 @@ struct pxa3xx_nand_info { unsigned int oob_size; int retcode; + /* cached register value */ + uint32_t reg_ndcr; + uint32_t ndtr0cs0; + uint32_t ndtr1cs0; + /* generated NDCBx register values */ uint32_t ndcb0; uint32_t ndcb1; uint32_t ndcb2; + uint32_t ndcb3; }; static bool use_dma = 1; module_param(use_dma, bool, 0444); MODULE_PARM_DESC(use_dma, "enable DMA for data transferring to/from NAND HW"); -/* - * Default NAND flash controller configuration setup by the - * bootloader. This configuration is used only when pdata->keep_config is set - */ -static struct pxa3xx_nand_cmdset default_cmdset = { - .read1 = 0x3000, - .read2 = 0x0050, - .program = 0x1080, - .read_status = 0x0070, - .read_id = 0x0090, - .erase = 0xD060, - .reset = 0x00FF, - .lock = 0x002A, - .unlock = 0x2423, - .lock_status = 0x007A, -}; - static struct pxa3xx_nand_timing timing[] = { { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, @@ -230,8 +234,6 @@ static struct pxa3xx_nand_flash builtin_flash_types[] = { /* Define a default flash type setting serve as flash detecting only */ #define DEFAULT_FLASH_TYPE (&builtin_flash_types[0]) -const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL}; - #define NDTR0_tCH(c) (min((c), 7) << 19) #define NDTR0_tCS(c) (min((c), 7) << 16) #define NDTR0_tWH(c) (min((c), 7) << 11) @@ -264,8 +266,8 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); - host->ndtr0cs0 = ndtr0; - host->ndtr1cs0 = ndtr1; + info->ndtr0cs0 = ndtr0; + info->ndtr1cs0 = ndtr1; nand_writel(info, NDTR0CS0, ndtr0); nand_writel(info, NDTR1CS0, ndtr1); } @@ -273,7 +275,7 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) { struct pxa3xx_nand_host *host = info->host[info->cs]; - int oob_enable = host->reg_ndcr & NDCR_SPARE_EN; + int oob_enable = info->reg_ndcr & NDCR_SPARE_EN; info->data_size = host->page_size; if (!oob_enable) { @@ -299,12 +301,25 @@ static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info) */ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) { - struct pxa3xx_nand_host *host = info->host[info->cs]; uint32_t ndcr; - ndcr = host->reg_ndcr; - ndcr |= info->use_ecc ? NDCR_ECC_EN : 0; - ndcr |= info->use_dma ? NDCR_DMA_EN : 0; + ndcr = info->reg_ndcr; + + if (info->use_ecc) + ndcr |= NDCR_ECC_EN; + else + ndcr &= ~NDCR_ECC_EN; + + if (info->use_dma) + ndcr |= NDCR_DMA_EN; + else + ndcr &= ~NDCR_DMA_EN; + + if (info->use_spare) + ndcr |= NDCR_SPARE_EN; + else + ndcr &= ~NDCR_SPARE_EN; + ndcr |= NDCR_ND_RUN; /* clear status bits and run */ @@ -333,7 +348,8 @@ static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info) nand_writel(info, NDSR, NDSR_MASK); } -static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) +static void __maybe_unused +enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) { uint32_t ndcr; @@ -373,6 +389,7 @@ static void handle_data_pio(struct pxa3xx_nand_info *info) } } +#ifdef ARCH_HAS_DMA static void start_data_dma(struct pxa3xx_nand_info *info) { struct pxa_dma_desc *desc = info->data_desc; @@ -419,6 +436,10 @@ static void pxa3xx_nand_data_dma_irq(int channel, void *data) enable_int(info, NDCR_INT_MASK); nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); } +#else +static void start_data_dma(struct pxa3xx_nand_info *info) +{} +#endif static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) { @@ -467,9 +488,22 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) nand_writel(info, NDSR, NDSR_WRCMDREQ); status &= ~NDSR_WRCMDREQ; info->state = STATE_CMD_HANDLE; + + /* + * Command buffer registers NDCB{0-2} (and optionally NDCB3) + * must be loaded by writing directly either 12 or 16 + * bytes directly to NDCB0, four bytes at a time. + * + * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored + * but each NDCBx register can be read. + */ nand_writel(info, NDCB0, info->ndcb0); nand_writel(info, NDCB0, info->ndcb1); nand_writel(info, NDCB0, info->ndcb2); + + /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ + if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) + nand_writel(info, NDCB0, info->ndcb3); } /* clear NDSR to let the controller exit the IRQ */ @@ -491,7 +525,6 @@ static inline int is_buf_blank(uint8_t *buf, size_t len) static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, uint16_t column, int page_addr) { - uint16_t cmd; int addr_cycle, exec_cmd; struct pxa3xx_nand_host *host; struct mtd_info *mtd; @@ -506,6 +539,8 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, info->buf_count = 0; info->oob_size = 0; info->use_ecc = 0; + info->use_spare = 1; + info->use_dma = (use_dma) ? 1 : 0; info->is_ready = 0; info->retcode = ERR_NONE; if (info->cs != 0) @@ -520,12 +555,16 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, case NAND_CMD_READOOB: pxa3xx_set_datasize(info); break; + case NAND_CMD_PARAM: + info->use_spare = 0; + break; case NAND_CMD_SEQIN: exec_cmd = 0; break; default: info->ndcb1 = 0; info->ndcb2 = 0; + info->ndcb3 = 0; break; } @@ -535,21 +574,17 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, switch (command) { case NAND_CMD_READOOB: case NAND_CMD_READ0: - cmd = host->cmdset->read1; + info->buf_start = column; + info->ndcb0 |= NDCB0_CMD_TYPE(0) + | addr_cycle + | NAND_CMD_READ0; + if (command == NAND_CMD_READOOB) - info->buf_start = mtd->writesize + column; - else - info->buf_start = column; + info->buf_start += mtd->writesize; - if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) - info->ndcb0 |= NDCB0_CMD_TYPE(0) - | addr_cycle - | (cmd & NDCB0_CMD1_MASK); - else - info->ndcb0 |= NDCB0_CMD_TYPE(0) - | NDCB0_DBC - | addr_cycle - | cmd; + /* Second command setting for large pages */ + if (host->page_size >= PAGE_CHUNK_SIZE) + info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); case NAND_CMD_SEQIN: /* small page addr setting */ @@ -580,49 +615,58 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, break; } - cmd = host->cmdset->program; info->ndcb0 |= NDCB0_CMD_TYPE(0x1) | NDCB0_AUTO_RS | NDCB0_ST_ROW_EN | NDCB0_DBC - | cmd + | (NAND_CMD_PAGEPROG << 8) + | NAND_CMD_SEQIN | addr_cycle; break; + case NAND_CMD_PARAM: + info->buf_count = 256; + info->ndcb0 |= NDCB0_CMD_TYPE(0) + | NDCB0_ADDR_CYC(1) + | NDCB0_LEN_OVRD + | command; + info->ndcb1 = (column & 0xFF); + info->ndcb3 = 256; + info->data_size = 256; + break; + case NAND_CMD_READID: - cmd = host->cmdset->read_id; info->buf_count = host->read_id_bytes; info->ndcb0 |= NDCB0_CMD_TYPE(3) | NDCB0_ADDR_CYC(1) - | cmd; + | command; + info->ndcb1 = (column & 0xFF); info->data_size = 8; break; case NAND_CMD_STATUS: - cmd = host->cmdset->read_status; info->buf_count = 1; info->ndcb0 |= NDCB0_CMD_TYPE(4) | NDCB0_ADDR_CYC(1) - | cmd; + | command; info->data_size = 8; break; case NAND_CMD_ERASE1: - cmd = host->cmdset->erase; info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3) | NDCB0_DBC - | cmd; + | (NAND_CMD_ERASE2 << 8) + | NAND_CMD_ERASE1; info->ndcb1 = page_addr; info->ndcb2 = 0; break; case NAND_CMD_RESET: - cmd = host->cmdset->reset; info->ndcb0 |= NDCB0_CMD_TYPE(5) - | cmd; + | command; break; @@ -652,7 +696,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, * "byte" address into a "word" address appropriate * for indexing a word-oriented device */ - if (host->reg_ndcr & NDCR_DWIDTH_M) + if (info->reg_ndcr & NDCR_DWIDTH_M) column /= 2; /* @@ -662,8 +706,8 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, */ if (info->cs != host->cs) { info->cs = host->cs; - nand_writel(info, NDTR0CS0, host->ndtr0cs0); - nand_writel(info, NDTR1CS0, host->ndtr1cs0); + nand_writel(info, NDTR0CS0, info->ndtr0cs0); + nand_writel(info, NDTR1CS0, info->ndtr1cs0); } info->state = STATE_PREPARED; @@ -803,7 +847,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, const struct pxa3xx_nand_flash *f) { struct platform_device *pdev = info->pdev; - struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; + struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); struct pxa3xx_nand_host *host = info->host[info->cs]; uint32_t ndcr = 0x0; /* enable all interrupts */ @@ -818,7 +862,6 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, } /* calculate flash information */ - host->cmdset = &default_cmdset; host->page_size = f->page_size; host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; @@ -840,7 +883,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); ndcr |= NDCR_SPARE_EN; /* enable spare by default */ - host->reg_ndcr = ndcr; + info->reg_ndcr = ndcr; pxa3xx_nand_set_timing(host, f->timing); return 0; @@ -863,12 +906,9 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) host->read_id_bytes = 2; } - host->reg_ndcr = ndcr & ~NDCR_INT_MASK; - host->cmdset = &default_cmdset; - - host->ndtr0cs0 = nand_readl(info, NDTR0CS0); - host->ndtr1cs0 = nand_readl(info, NDTR1CS0); - + info->reg_ndcr = ndcr & ~NDCR_INT_MASK; + info->ndtr0cs0 = nand_readl(info, NDTR0CS0); + info->ndtr1cs0 = nand_readl(info, NDTR1CS0); return 0; } @@ -878,6 +918,7 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) */ #define MAX_BUFF_SIZE PAGE_SIZE +#ifdef ARCH_HAS_DMA static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) { struct platform_device *pdev = info->pdev; @@ -912,6 +953,32 @@ static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) return 0; } +static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) +{ + struct platform_device *pdev = info->pdev; + if (use_dma) { + pxa_free_dma(info->data_dma_ch); + dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, + info->data_buff, info->data_buff_phys); + } else { + kfree(info->data_buff); + } +} +#else +static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) +{ + info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL); + if (info->data_buff == NULL) + return -ENOMEM; + return 0; +} + +static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info) +{ + kfree(info->data_buff); +} +#endif + static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info) { struct mtd_info *mtd; @@ -934,7 +1001,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) struct pxa3xx_nand_host *host = mtd->priv; struct pxa3xx_nand_info *info = host->info_data; struct platform_device *pdev = info->pdev; - struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; + struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL; const struct pxa3xx_nand_flash *f = NULL; struct nand_chip *chip = mtd->priv; @@ -1003,7 +1070,7 @@ KEEP_CONFIG: chip->ecc.size = host->page_size; chip->ecc.strength = 1; - if (host->reg_ndcr & NDCR_DWIDTH_M) + if (info->reg_ndcr & NDCR_DWIDTH_M) chip->options |= NAND_BUSWIDTH_16; if (nand_scan_ident(mtd, 1, def)) @@ -1019,8 +1086,6 @@ KEEP_CONFIG: host->row_addr_cycles = 3; else host->row_addr_cycles = 2; - - mtd->name = mtd_names[0]; return nand_scan_tail(mtd); } @@ -1034,13 +1099,11 @@ static int alloc_nand_resource(struct platform_device *pdev) struct resource *r; int ret, irq, cs; - pdata = pdev->dev.platform_data; - info = kzalloc(sizeof(*info) + (sizeof(*mtd) + - sizeof(*host)) * pdata->num_cs, GFP_KERNEL); - if (!info) { - dev_err(&pdev->dev, "failed to allocate memory\n"); + pdata = dev_get_platdata(&pdev->dev); + info = devm_kzalloc(&pdev->dev, sizeof(*info) + (sizeof(*mtd) + + sizeof(*host)) * pdata->num_cs, GFP_KERNEL); + if (!info) return -ENOMEM; - } info->pdev = pdev; for (cs = 0; cs < pdata->num_cs; cs++) { @@ -1069,72 +1132,64 @@ static int alloc_nand_resource(struct platform_device *pdev) spin_lock_init(&chip->controller->lock); init_waitqueue_head(&chip->controller->wq); - info->clk = clk_get(&pdev->dev, NULL); + info->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(info->clk)) { dev_err(&pdev->dev, "failed to get nand clock\n"); - ret = PTR_ERR(info->clk); - goto fail_free_mtd; + return PTR_ERR(info->clk); } - clk_enable(info->clk); - - /* - * This is a dirty hack to make this driver work from devicetree - * bindings. It can be removed once we have a prober DMA controller - * framework for DT. - */ - if (pdev->dev.of_node && cpu_is_pxa3xx()) { - info->drcmr_dat = 97; - info->drcmr_cmd = 99; - } else { - r = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (r == NULL) { - dev_err(&pdev->dev, "no resource defined for data DMA\n"); - ret = -ENXIO; - goto fail_put_clk; - } - info->drcmr_dat = r->start; + ret = clk_prepare_enable(info->clk); + if (ret < 0) + return ret; - r = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (r == NULL) { - dev_err(&pdev->dev, "no resource defined for command DMA\n"); - ret = -ENXIO; - goto fail_put_clk; + if (use_dma) { + /* + * This is a dirty hack to make this driver work from + * devicetree bindings. It can be removed once we have + * a prober DMA controller framework for DT. + */ + if (pdev->dev.of_node && + of_machine_is_compatible("marvell,pxa3xx")) { + info->drcmr_dat = 97; + info->drcmr_cmd = 99; + } else { + r = platform_get_resource(pdev, IORESOURCE_DMA, 0); + if (r == NULL) { + dev_err(&pdev->dev, + "no resource defined for data DMA\n"); + ret = -ENXIO; + goto fail_disable_clk; + } + info->drcmr_dat = r->start; + + r = platform_get_resource(pdev, IORESOURCE_DMA, 1); + if (r == NULL) { + dev_err(&pdev->dev, + "no resource defined for cmd DMA\n"); + ret = -ENXIO; + goto fail_disable_clk; + } + info->drcmr_cmd = r->start; } - info->drcmr_cmd = r->start; } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no IRQ resource defined\n"); ret = -ENXIO; - goto fail_put_clk; + goto fail_disable_clk; } r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (r == NULL) { - dev_err(&pdev->dev, "no IO memory resource defined\n"); - ret = -ENODEV; - goto fail_put_clk; - } - - r = request_mem_region(r->start, resource_size(r), pdev->name); - if (r == NULL) { - dev_err(&pdev->dev, "failed to request memory resource\n"); - ret = -EBUSY; - goto fail_put_clk; - } - - info->mmio_base = ioremap(r->start, resource_size(r)); - if (info->mmio_base == NULL) { - dev_err(&pdev->dev, "ioremap() failed\n"); - ret = -ENODEV; - goto fail_free_res; + info->mmio_base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(info->mmio_base)) { + ret = PTR_ERR(info->mmio_base); + goto fail_disable_clk; } info->mmio_phys = r->start; ret = pxa3xx_nand_init_buff(info); if (ret) - goto fail_free_io; + goto fail_disable_clk; /* initialize all interrupts to be disabled */ disable_int(info, NDSR_MASK); @@ -1152,21 +1207,9 @@ static int alloc_nand_resource(struct platform_device *pdev) fail_free_buf: free_irq(irq, info); - if (use_dma) { - pxa_free_dma(info->data_dma_ch); - dma_free_coherent(&pdev->dev, MAX_BUFF_SIZE, - info->data_buff, info->data_buff_phys); - } else - kfree(info->data_buff); -fail_free_io: - iounmap(info->mmio_base); -fail_free_res: - release_mem_region(r->start, resource_size(r)); -fail_put_clk: - clk_disable(info->clk); - clk_put(info->clk); -fail_free_mtd: - kfree(info); + pxa3xx_nand_free_buff(info); +fail_disable_clk: + clk_disable_unprepare(info->clk); return ret; } @@ -1174,44 +1217,48 @@ static int pxa3xx_nand_remove(struct platform_device *pdev) { struct pxa3xx_nand_info *info = platform_get_drvdata(pdev); struct pxa3xx_nand_platform_data *pdata; - struct resource *r; int irq, cs; if (!info) return 0; - pdata = pdev->dev.platform_data; - platform_set_drvdata(pdev, NULL); + pdata = dev_get_platdata(&pdev->dev); irq = platform_get_irq(pdev, 0); if (irq >= 0) free_irq(irq, info); - if (use_dma) { - pxa_free_dma(info->data_dma_ch); - dma_free_writecombine(&pdev->dev, MAX_BUFF_SIZE, - info->data_buff, info->data_buff_phys); - } else - kfree(info->data_buff); - - iounmap(info->mmio_base); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(r->start, resource_size(r)); + pxa3xx_nand_free_buff(info); - clk_disable(info->clk); - clk_put(info->clk); + clk_disable_unprepare(info->clk); for (cs = 0; cs < pdata->num_cs; cs++) nand_release(info->host[cs]->mtd); - kfree(info); return 0; } #ifdef CONFIG_OF static struct of_device_id pxa3xx_nand_dt_ids[] = { - { .compatible = "marvell,pxa3xx-nand" }, + { + .compatible = "marvell,pxa3xx-nand", + .data = (void *)PXA3XX_NAND_VARIANT_PXA, + }, + { + .compatible = "marvell,armada370-nand", + .data = (void *)PXA3XX_NAND_VARIANT_ARMADA370, + }, {} }; -MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); +MODULE_DEVICE_TABLE(of, pxa3xx_nand_dt_ids); + +static enum pxa3xx_nand_variant +pxa3xx_nand_get_variant(struct platform_device *pdev) +{ + const struct of_device_id *of_id = + of_match_device(pxa3xx_nand_dt_ids, &pdev->dev); + if (!of_id) + return PXA3XX_NAND_VARIANT_PXA; + return (enum pxa3xx_nand_variant)of_id->data; +} static int pxa3xx_nand_probe_dt(struct platform_device *pdev) { @@ -1251,11 +1298,18 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) struct pxa3xx_nand_info *info; int ret, cs, probe_success; +#ifndef ARCH_HAS_DMA + if (use_dma) { + use_dma = 0; + dev_warn(&pdev->dev, + "This platform can't do DMA on this device\n"); + } +#endif ret = pxa3xx_nand_probe_dt(pdev); if (ret) return ret; - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); if (!pdata) { dev_err(&pdev->dev, "no platform data defined\n"); return -ENODEV; @@ -1268,10 +1322,14 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) } info = platform_get_drvdata(pdev); + info->variant = pxa3xx_nand_get_variant(pdev); probe_success = 0; for (cs = 0; cs < pdata->num_cs; cs++) { + struct mtd_info *mtd = info->host[cs]->mtd; + + mtd->name = pdev->name; info->cs = cs; - ret = pxa3xx_nand_scan(info->host[cs]->mtd); + ret = pxa3xx_nand_scan(mtd); if (ret) { dev_warn(&pdev->dev, "failed to scan nand at cs %d\n", cs); @@ -1279,7 +1337,7 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) } ppdata.of_node = pdev->dev.of_node; - ret = mtd_device_parse_register(info->host[cs]->mtd, NULL, + ret = mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts[cs], pdata->nr_parts[cs]); if (!ret) @@ -1302,7 +1360,7 @@ static int pxa3xx_nand_suspend(struct platform_device *pdev, pm_message_t state) struct mtd_info *mtd; int cs; - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); if (info->state) { dev_err(&pdev->dev, "driver busy, state = %d\n", info->state); return -EAGAIN; @@ -1323,7 +1381,7 @@ static int pxa3xx_nand_resume(struct platform_device *pdev) struct mtd_info *mtd; int cs; - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); /* We don't want to handle interrupt without calling mtd routine */ disable_int(info, NDCR_INT_MASK); diff --git a/drivers/mtd/nand/r852.c b/drivers/mtd/nand/r852.c index 4495f85..9dcf02d 100644 --- a/drivers/mtd/nand/r852.c +++ b/drivers/mtd/nand/r852.c @@ -229,7 +229,7 @@ static void r852_do_dma(struct r852_device *dev, uint8_t *buf, int do_read) /* * Program data lines of the nand chip to send data to it */ -void r852_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +static void r852_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) { struct r852_device *dev = r852_get_dev(mtd); uint32_t reg; @@ -261,7 +261,7 @@ void r852_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) /* * Read data lines of the nand chip to retrieve data */ -void r852_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +static void r852_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) { struct r852_device *dev = r852_get_dev(mtd); uint32_t reg; @@ -312,7 +312,7 @@ static uint8_t r852_read_byte(struct mtd_info *mtd) /* * Control several chip lines & send commands */ -void r852_cmdctl(struct mtd_info *mtd, int dat, unsigned int ctrl) +static void r852_cmdctl(struct mtd_info *mtd, int dat, unsigned int ctrl) { struct r852_device *dev = r852_get_dev(mtd); @@ -357,7 +357,7 @@ void r852_cmdctl(struct mtd_info *mtd, int dat, unsigned int ctrl) * Wait till card is ready. * based on nand_wait, but returns errors on DMA error */ -int r852_wait(struct mtd_info *mtd, struct nand_chip *chip) +static int r852_wait(struct mtd_info *mtd, struct nand_chip *chip) { struct r852_device *dev = chip->priv; @@ -386,7 +386,7 @@ int r852_wait(struct mtd_info *mtd, struct nand_chip *chip) * Check if card is ready */ -int r852_ready(struct mtd_info *mtd) +static int r852_ready(struct mtd_info *mtd) { struct r852_device *dev = r852_get_dev(mtd); return !(r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_BUSY); @@ -397,7 +397,7 @@ int r852_ready(struct mtd_info *mtd) * Set ECC engine mode */ -void r852_ecc_hwctl(struct mtd_info *mtd, int mode) +static void r852_ecc_hwctl(struct mtd_info *mtd, int mode) { struct r852_device *dev = r852_get_dev(mtd); @@ -429,7 +429,7 @@ void r852_ecc_hwctl(struct mtd_info *mtd, int mode) * Calculate ECC, only used for writes */ -int r852_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, +static int r852_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { struct r852_device *dev = r852_get_dev(mtd); @@ -461,7 +461,7 @@ int r852_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, * Correct the data using ECC, hw did almost everything for us */ -int r852_ecc_correct(struct mtd_info *mtd, uint8_t *dat, +static int r852_ecc_correct(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc) { uint16_t ecc_reg; @@ -529,7 +529,7 @@ static int r852_read_oob(struct mtd_info *mtd, struct nand_chip *chip, * Start the nand engine */ -void r852_engine_enable(struct r852_device *dev) +static void r852_engine_enable(struct r852_device *dev) { if (r852_read_reg_dword(dev, R852_HW) & R852_HW_UNKNOWN) { r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON); @@ -547,7 +547,7 @@ void r852_engine_enable(struct r852_device *dev) * Stop the nand engine */ -void r852_engine_disable(struct r852_device *dev) +static void r852_engine_disable(struct r852_device *dev) { r852_write_reg_dword(dev, R852_HW, 0); r852_write_reg(dev, R852_CTL, R852_CTL_RESET); @@ -557,7 +557,7 @@ void r852_engine_disable(struct r852_device *dev) * Test if card is present */ -void r852_card_update_present(struct r852_device *dev) +static void r852_card_update_present(struct r852_device *dev) { unsigned long flags; uint8_t reg; @@ -572,7 +572,7 @@ void r852_card_update_present(struct r852_device *dev) * Update card detection IRQ state according to current card state * which is read in r852_card_update_present */ -void r852_update_card_detect(struct r852_device *dev) +static void r852_update_card_detect(struct r852_device *dev) { int card_detect_reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE); dev->card_unstable = 0; @@ -586,8 +586,8 @@ void r852_update_card_detect(struct r852_device *dev) r852_write_reg(dev, R852_CARD_IRQ_ENABLE, card_detect_reg); } -ssize_t r852_media_type_show(struct device *sys_dev, - struct device_attribute *attr, char *buf) +static ssize_t r852_media_type_show(struct device *sys_dev, + struct device_attribute *attr, char *buf) { struct mtd_info *mtd = container_of(sys_dev, struct mtd_info, dev); struct r852_device *dev = r852_get_dev(mtd); @@ -597,11 +597,11 @@ ssize_t r852_media_type_show(struct device *sys_dev, return strlen(data); } -DEVICE_ATTR(media_type, S_IRUGO, r852_media_type_show, NULL); +static DEVICE_ATTR(media_type, S_IRUGO, r852_media_type_show, NULL); /* Detect properties of card in slot */ -void r852_update_media_status(struct r852_device *dev) +static void r852_update_media_status(struct r852_device *dev) { uint8_t reg; unsigned long flags; @@ -630,7 +630,7 @@ void r852_update_media_status(struct r852_device *dev) * Register the nand device * Called when the card is detected */ -int r852_register_nand_device(struct r852_device *dev) +static int r852_register_nand_device(struct r852_device *dev) { dev->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL); @@ -668,7 +668,7 @@ error1: * Unregister the card */ -void r852_unregister_nand_device(struct r852_device *dev) +static void r852_unregister_nand_device(struct r852_device *dev) { if (!dev->card_registred) return; @@ -682,7 +682,7 @@ void r852_unregister_nand_device(struct r852_device *dev) } /* Card state updater */ -void r852_card_detect_work(struct work_struct *work) +static void r852_card_detect_work(struct work_struct *work) { struct r852_device *dev = container_of(work, struct r852_device, card_detect_work.work); @@ -821,7 +821,7 @@ out: return ret; } -int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) +static int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) { int error; struct nand_chip *chip; @@ -961,7 +961,7 @@ error1: return error; } -void r852_remove(struct pci_dev *pci_dev) +static void r852_remove(struct pci_dev *pci_dev) { struct r852_device *dev = pci_get_drvdata(pci_dev); @@ -992,7 +992,7 @@ void r852_remove(struct pci_dev *pci_dev) pci_disable_device(pci_dev); } -void r852_shutdown(struct pci_dev *pci_dev) +static void r852_shutdown(struct pci_dev *pci_dev) { struct r852_device *dev = pci_get_drvdata(pci_dev); @@ -1002,7 +1002,7 @@ void r852_shutdown(struct pci_dev *pci_dev) pci_disable_device(pci_dev); } -#ifdef CONFIG_PM +#ifdef CONFIG_PM_SLEEP static int r852_suspend(struct device *device) { struct r852_device *dev = pci_get_drvdata(to_pci_dev(device)); @@ -1055,9 +1055,6 @@ static int r852_resume(struct device *device) r852_update_card_detect(dev); return 0; } -#else -#define r852_suspend NULL -#define r852_resume NULL #endif static const struct pci_device_id r852_pci_id_tbl[] = { diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index d65afd2..d65cbe9 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -150,7 +150,7 @@ static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) { - return dev->dev.platform_data; + return dev_get_platdata(&dev->dev); } static inline int allow_clk_suspend(struct s3c2410_nand_info *info) @@ -697,8 +697,6 @@ static int s3c24xx_nand_remove(struct platform_device *pdev) { struct s3c2410_nand_info *info = to_nand_info(pdev); - platform_set_drvdata(pdev, NULL); - if (info == NULL) return 0; diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c index e57e18e..a3c84eb 100644 --- a/drivers/mtd/nand/sh_flctl.c +++ b/drivers/mtd/nand/sh_flctl.c @@ -137,7 +137,7 @@ static void flctl_setup_dma(struct sh_flctl *flctl) dma_cap_mask_t mask; struct dma_slave_config cfg; struct platform_device *pdev = flctl->pdev; - struct sh_flctl_platform_data *pdata = pdev->dev.platform_data; + struct sh_flctl_platform_data *pdata = dev_get_platdata(&pdev->dev); int ret; if (!pdata) @@ -1131,7 +1131,7 @@ static int flctl_probe(struct platform_device *pdev) if (pdev->dev.of_node) pdata = flctl_parse_dt(&pdev->dev); else - pdata = pdev->dev.platform_data; + pdata = dev_get_platdata(&pdev->dev); if (!pdata) { dev_err(&pdev->dev, "no setup data defined\n"); diff --git a/drivers/mtd/nand/sharpsl.c b/drivers/mtd/nand/sharpsl.c index 127bc42..87908d7 100644 --- a/drivers/mtd/nand/sharpsl.c +++ b/drivers/mtd/nand/sharpsl.c @@ -112,7 +112,7 @@ static int sharpsl_nand_probe(struct platform_device *pdev) struct resource *r; int err = 0; struct sharpsl_nand *sharpsl; - struct sharpsl_nand_platform_data *data = pdev->dev.platform_data; + struct sharpsl_nand_platform_data *data = dev_get_platdata(&pdev->dev); if (!data) { dev_err(&pdev->dev, "no platform data!\n"); @@ -194,7 +194,6 @@ err_add: nand_release(&sharpsl->mtd); err_scan: - platform_set_drvdata(pdev, NULL); iounmap(sharpsl->io); err_ioremap: err_get_res: @@ -212,8 +211,6 @@ static int sharpsl_nand_remove(struct platform_device *pdev) /* Release resources, unregister device */ nand_release(&sharpsl->mtd); - platform_set_drvdata(pdev, NULL); - iounmap(sharpsl->io); /* Free the MTD device structure */ diff --git a/drivers/mtd/nand/sm_common.c b/drivers/mtd/nand/sm_common.c index e8181ed..e06b5e5 100644 --- a/drivers/mtd/nand/sm_common.c +++ b/drivers/mtd/nand/sm_common.c @@ -42,7 +42,7 @@ static int sm_block_markbad(struct mtd_info *mtd, loff_t ofs) { struct mtd_oob_ops ops; struct sm_oob oob; - int ret, error = 0; + int ret; memset(&oob, -1, SM_OOB_SIZE); oob.block_status = 0x0F; @@ -61,11 +61,10 @@ static int sm_block_markbad(struct mtd_info *mtd, loff_t ofs) printk(KERN_NOTICE "sm_common: can't mark sector at %i as bad\n", (int)ofs); - error = -EIO; - } else - mtd->ecc_stats.badblocks++; + return -EIO; + } - return error; + return 0; } static struct nand_flash_dev nand_smartmedia_flash_ids[] = { diff --git a/drivers/mtd/nand/tmio_nand.c b/drivers/mtd/nand/tmio_nand.c index 508e9e0..396530d 100644 --- a/drivers/mtd/nand/tmio_nand.c +++ b/drivers/mtd/nand/tmio_nand.c @@ -357,7 +357,7 @@ static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio) static int tmio_probe(struct platform_device *dev) { - struct tmio_nand_data *data = dev->dev.platform_data; + struct tmio_nand_data *data = dev_get_platdata(&dev->dev); struct resource *fcr = platform_get_resource(dev, IORESOURCE_MEM, 0); struct resource *ccr = platform_get_resource(dev, diff --git a/drivers/mtd/nand/txx9ndfmc.c b/drivers/mtd/nand/txx9ndfmc.c index 7ed654c..235714a 100644 --- a/drivers/mtd/nand/txx9ndfmc.c +++ b/drivers/mtd/nand/txx9ndfmc.c @@ -87,7 +87,7 @@ static struct platform_device *mtd_to_platdev(struct mtd_info *mtd) static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg) { struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); - struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; + struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); return drvdata->base + (reg << plat->shift); } @@ -138,7 +138,7 @@ static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd, struct nand_chip *chip = mtd->priv; struct txx9ndfmc_priv *txx9_priv = chip->priv; struct platform_device *dev = txx9_priv->dev; - struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; + struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); if (ctrl & NAND_CTRL_CHANGE) { u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); @@ -225,7 +225,7 @@ static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode) static void txx9ndfmc_initialize(struct platform_device *dev) { - struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; + struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); int tmout = 100; @@ -274,19 +274,17 @@ static int txx9ndfmc_nand_scan(struct mtd_info *mtd) static int __init txx9ndfmc_probe(struct platform_device *dev) { - struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; + struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev); int hold, spw; int i; struct txx9ndfmc_drvdata *drvdata; unsigned long gbusclk = plat->gbus_clock; struct resource *res; - res = platform_get_resource(dev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; + res = platform_get_resource(dev, IORESOURCE_MEM, 0); drvdata->base = devm_ioremap_resource(&dev->dev, res); if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base); @@ -387,7 +385,6 @@ static int __exit txx9ndfmc_remove(struct platform_device *dev) struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); int i; - platform_set_drvdata(dev, NULL); if (!drvdata) return 0; for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { |