diff options
| author | b44839 <b44839@b44839-VirtualBox.(none)> | 2014-09-30 10:41:08 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:37:59 (GMT) |
| commit | 6962d5c31cf158ce11a10ea8e4a827e35302c563 (patch) | |
| tree | 15f8faccc81462f51a64e434dbd0c470fe5d85f3 /drivers/mtd | |
| parent | 5481b9b61ad7b09fdc9426e62b9040a3978d50bc (diff) | |
| download | linux-fsl-qoriq-6962d5c31cf158ce11a10ea8e4a827e35302c563.tar.xz | |
driver/memory:Move Freescale IFC driver to a common driver
Freescale IFC controller has been used for mpc8xxx.
It will be used for ARM-based SoC as well. This patch
moves the driver to driver/memory and fix the header
file includes.
Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall()
to make sure this module has been loaded before
MTD partition parsing starts.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Cherry-picked from:d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc
Change-Id: I3cc83c716adf27a4988b818d57706980dbbefdea
Reviewed-on: http://git.am.freescale.net:8181/20970
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/fsl_ifc_nand.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 8639a42..12af7fc 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -29,7 +29,8 @@ #include <linux/mtd/nand.h> #include <linux/mtd/partitions.h> #include <linux/mtd/nand_ecc.h> -#include <asm/fsl_ifc.h> +#include <linux/of_address.h> +#include <linux/fsl_ifc.h> #define FSL_IFC_V1_1_0 0x01010000 #define ERR_BYTE 0xFF /* Value returned for read @@ -591,7 +592,8 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, * The chip always seems to report that it is * write-protected, even when it is not. */ - setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP); + iowrite8((ioread8(ifc_nand_ctrl->addr) | (NAND_STATUS_WP)), + ifc_nand_ctrl->addr); return; case NAND_CMD_RESET: @@ -654,7 +656,7 @@ static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd) * next byte. */ if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) - return in_8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]); + return ioread8(&ifc_nand_ctrl->addr[ifc_nand_ctrl->index++]); dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); return ERR_BYTE; @@ -675,7 +677,7 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) * next byte. */ if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { - data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl-> + data = ioread16be((uint16_t __iomem *)&ifc_nand_ctrl-> addr[ifc_nand_ctrl->index]); ifc_nand_ctrl->index += 2; return (uint8_t) data; |