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authorCloud Ren <cjren@qca.qualcomm.com>2012-07-19 17:01:58 (GMT)
committerDavid S. Miller <davem@davemloft.net>2012-07-20 18:21:18 (GMT)
commitfa0afcd10951afad2022dda09777d2bf70cdab3d (patch)
tree3f74c4d6d407f0b4a23e291ba56652c5f3125522 /drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
parentb09e786bd1dd66418b69348cb110f3a64764626a (diff)
downloadlinux-fsl-qoriq-fa0afcd10951afad2022dda09777d2bf70cdab3d.tar.xz
atl1c: fix issue of io access mode for AR8152 v2.1
When io access mode is enabled by BOOTROM or BIOS for AR8152 v2.1, the register can't be read/write by memory access mode. Clearing Bit 8 of Register 0x21c could fixed the issue. Signed-off-by: Cloud Ren <cjren@qca.qualcomm.com> Cc: stable <stable@vger.kernel.org> Signed-off-by: xiong <xiong@qca.qualcomm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/atheros/atl1c/atl1c_hw.h')
-rw-r--r--drivers/net/ethernet/atheros/atl1c/atl1c_hw.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
index 17d935b..21d8c4d 100644
--- a/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
+++ b/drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
@@ -74,6 +74,8 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
#define L2CB_V10 0xc0
#define L2CB_V11 0xc1
+#define L2CB_V20 0xc0
+#define L2CB_V21 0xc1
/* register definition */
#define REG_DEVICE_CAP 0x5C
@@ -87,6 +89,9 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
#define LINK_CTRL_L1_EN 0x02
#define LINK_CTRL_EXT_SYNC 0x80
+#define REG_PCIE_IND_ACC_ADDR 0x80
+#define REG_PCIE_IND_ACC_DATA 0x84
+
#define REG_DEV_SERIALNUM_CTRL 0x200
#define REG_DEV_MAC_SEL_MASK 0x0 /* 0:EUI; 1:MAC */
#define REG_DEV_MAC_SEL_SHIFT 0