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| author | Cristian Sovaiala <cristian.sovaiala@freescale.com> | 2013-10-10 15:45:53 (GMT) |
|---|---|---|
| committer | J. German Rivera <German.Rivera@freescale.com> | 2013-10-29 20:44:11 (GMT) |
| commit | 5121e5a4941577a18aaee5d4769f97aec6f16030 (patch) | |
| tree | 0379f3539f62244ed32012d9a04556694cb600c2 /drivers/net/ethernet/freescale/dpa | |
| parent | 289b323d8c8b9fea1a6f42993ccc40e8ab92c6d3 (diff) | |
| download | linux-fsl-qoriq-5121e5a4941577a18aaee5d4769f97aec6f16030.tar.xz | |
dpaa_eth: Add pool channel in each affined portal's SDQCR
There might be CPUs which are not enabled at boottime, therefore
the pool channel is not currently set to the SDQCR of the affined
portals of those CPUs.
This means that the portals affined to the offline CPUs and which
are migrated to the boot CPU, will not issue interrupts to the
boot CPU in first instance and to the affined CPU (when this comes
online) in the second instance.
Therefore we set the pool channel to the SDQCR of each affined portal.
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Change-Id: I63f5649e0c2169617dff991f08dd872a435578a8
Reviewed-on: http://git.am.freescale.net:8181/5629
Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ruxandra Ioana Radulescu <ruxandra.radulescu@freescale.com>
Reviewed-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Diffstat (limited to 'drivers/net/ethernet/freescale/dpa')
| -rw-r--r-- | drivers/net/ethernet/freescale/dpa/dpaa_eth_common.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/net/ethernet/freescale/dpa/dpaa_eth_common.c b/drivers/net/ethernet/freescale/dpa/dpaa_eth_common.c index d4ded36..c599052 100644 --- a/drivers/net/ethernet/freescale/dpa/dpaa_eth_common.c +++ b/drivers/net/ethernet/freescale/dpa/dpaa_eth_common.c @@ -934,10 +934,11 @@ int dpaa_eth_add_channel(void *__arg) const cpumask_t *cpus = qman_affine_cpus(); u32 pool = QM_SDQCR_CHANNELS_POOL_CONV((u32)(unsigned long)__arg); int cpu; + struct qman_portal *portal; for_each_cpu(cpu, cpus) { - set_cpus_allowed_ptr(current, get_cpu_mask(cpu)); - qman_static_dequeue_add(pool); + portal = (struct qman_portal *)qman_get_affine_portal(cpu); + qman_p_static_dequeue_add(portal, pool); } return 0; } |