fmd: fmd21.1 integration

Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>

- PFC
  Adjustments for PFC configuration constraints and limitations related to
  port prefetch mode

- workaround ucode issues
  Fix the following HW erratas regarding discard/error frames on V3:

    FM_OP_NO_VSP_NO_RELEASE_ERRATA_FMAN_A006675 -
      Description: OP without VSP will cause buffer leaks when instructed to discard a frame.
      Workaround: FW will release the buffers.

    FM_ERROR_VSP_NO_MATCH_SW006 -
      Description: Any port with VSP enabled and multiple VSPs are configured
                   on this port can cause a situation where an error frame will
                   be enqueued to the error queue not with the default VSP.
      Workaround:  FW will replaced the current VSP with the default VSP
                   just before the frame is being enqueued to the error queue.

- Chosen-node new parameter support
  errors-to-discard
      Usage: optional
      Value type: <u32>
      Definition: Specifies which errors should be discarded.
        Errors that are not in the mask, will not be discarded;
        I.e. those errors will be enqueued and sent to the default error queue.

Change-Id: Ib468c67de88376e17d9c39ab5a0c8fc5b33b7b82
Reviewed-on: http://git.am.freescale.net:8181/2605
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Bucur Madalin-Cristian-B32716 <madalin.bucur@freescale.com>
Reviewed-by: Garg Vakul-B16394 <vakul@freescale.com>
Reviewed-by: Radulescu Ruxandra Ioana-B05472 <ruxandra.radulescu@freescale.com>
Reviewed-by: Chereji Marian-Cornel-R27762 <marian.chereji@freescale.com>
Reviewed-by: Wang Haiying-R54964 <Haiying.Wang@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>

8 files changed, 72 insertions, 168 deletions

diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.c b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.c
index 605a1aa..e6fdb3f 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.c
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2012 Freescale Semiconductor Inc.
+ * Copyright 2008-2013 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -30,11 +30,10 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-
 /******************************************************************************
  @File          dtsec.c
 
- @Description   FM dTSEC ...
+ @Description   FMan dTSEC driver
 *//***************************************************************************/
 
 #include "std_ext.h"
@@ -410,7 +409,8 @@ static t_Error GracefulStop(t_Dtsec *p_Dtsec, e_CommMode mode)
     }
 
     if (mode & e_COMM_MODE_TX)
-#if defined(FM_GTS_ERRATA_DTSEC_A004) || defined(FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012)
+#if defined(FM_GTS_ERRATA_DTSEC_A004) || \
+    defined(FM_GTS_AFTER_MAC_ABORTED_FRAME_ERRATA_DTSEC_A0012)
     if (p_Dtsec->fmMacControllerDriver.fmRevInfo.majorRev == 2)
         DBG(INFO, ("GTS not supported due to DTSEC_A004 errata."));
 #else  /* not defined(FM_GTS_ERRATA_DTSEC_A004) ||... */
@@ -1289,8 +1289,6 @@ static t_Error DtsecInit(t_Handle h_Dtsec)
         RETURN_ERROR(MAJOR, err, ("This DTSEC version does not support the required i/f mode"));
     }
 
-    DTSEC_MII_Init(h_Dtsec);
-
     if (ENET_INTERFACE_FROM_MODE(p_Dtsec->enetMode) == e_ENET_IF_SGMII)
     {
         uint16_t            tmpReg16;
diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.h b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.h
index 177bc45..c26f40c 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.h
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2012 Freescale Semiconductor Inc.
+ * Copyright 2008-2013 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -30,7 +30,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-
 /******************************************************************************
  @File          dtsec.h
 
diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.c b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.c
index 371e1f9..f9dff6f 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.c
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2012 Freescale Semiconductor Inc.
+ * Copyright 2008-2013 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -52,14 +52,16 @@ t_Error DTSEC_MII_WritePhyReg(t_Handle    h_Dtsec,
 {
     t_Dtsec              *p_Dtsec = (t_Dtsec *)h_Dtsec;
     struct dtsec_mii_reg *miiregs;
+    uint16_t              dtsec_freq;
     t_Error               err;
 
     SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
     SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
 
+    dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
     miiregs = p_Dtsec->p_MiiMemMap;
 
-    err = (t_Error)dtsec_mii_write_reg(miiregs, phyAddr, reg, data);
+    err = (t_Error)fman_dtsec_mii_write_reg(miiregs, phyAddr, reg, data, dtsec_freq);
 
     return err;
 }
@@ -72,14 +74,16 @@ t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec,
 {
     t_Dtsec               *p_Dtsec = (t_Dtsec *)h_Dtsec;
     struct dtsec_mii_reg  *miiregs;
+    uint16_t               dtsec_freq;
     t_Error                err;
 
     SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
     SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
 
+    dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
     miiregs = p_Dtsec->p_MiiMemMap;
 
-    err = (t_Error)dtsec_mii_read_reg(miiregs, phyAddr, reg, p_Data);
+    err = (t_Error)fman_dtsec_mii_read_reg(miiregs, phyAddr, reg, p_Data, dtsec_freq);
 
     if (*p_Data == 0xffff)
         RETURN_ERROR(MINOR, E_NO_DEVICE,
@@ -91,19 +95,3 @@ t_Error DTSEC_MII_ReadPhyReg(t_Handle h_Dtsec,
     return err;
 }
 
-t_Error DTSEC_MII_Init(t_Handle h_Dtsec)
-{
-    t_Dtsec                *p_Dtsec = (t_Dtsec *)h_Dtsec;
-    struct dtsec_mii_reg  *miiregs;
-    uint16_t dtsec_freq;
-
-    SANITY_CHECK_RETURN_ERROR(p_Dtsec, E_INVALID_HANDLE);
-    SANITY_CHECK_RETURN_ERROR(p_Dtsec->p_MiiMemMap, E_INVALID_HANDLE);
-
-    miiregs = p_Dtsec->p_MiiMemMap;
-    dtsec_freq = (uint16_t)(p_Dtsec->fmMacControllerDriver.clkFreq >> 1);
-
-    dtsec_mii_init(miiregs, dtsec_freq);
-
-    return E_OK;
-}
diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.h b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.h
index d5dd39a..75cc658 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.h
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/dtsec_mii_acc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2012 Freescale Semiconductor Inc.
+ * Copyright 2008-2013 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -30,7 +30,6 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-
 #ifndef __DTSEC_MII_ACC_H
 #define __DTSEC_MII_ACC_H
 
@@ -39,7 +38,5 @@
 
 t_Error DTSEC_MII_WritePhyReg(t_Handle h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t data);
 t_Error DTSEC_MII_ReadPhyReg(t_Handle  h_Dtsec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
-t_Error DTSEC_MII_Init(t_Handle h_Dtsec);
-
 
 #endif /* __DTSEC_MII_ACC_H */
diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fm_mac.c b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fm_mac.c
index f07b174..9050a77 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fm_mac.c
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fm_mac.c
@@ -350,9 +350,6 @@ t_Error FM_MAC_SetTxPauseFrames(t_Handle h_FmMac,
 
     SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
 
-    if ((priority != 0xFF) && FmGetTnumAgingPeriod(p_FmMacControllerDriver->h_Fm) == 0)
-        RETURN_ERROR(MAJOR, E_CONFLICT, ("Can't configure PFC when TNUM aging is disabled"));
-
     if (p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames)
         return p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames(h_FmMac,
                                                                   priority,
diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c
index b1b7bae..1831f09 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fman_dtsec_mii_acc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2012 Freescale Semiconductor Inc.
+ * Copyright 2008-2013 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -40,7 +40,8 @@
  * @dtsec_freq:		dtsec clock frequency (in Mhz)
  *
  * This function calculates the dtsec mii clock divider that determines
- * the MII MDC clock. MII MDC clock can work in the range of 2.5 to 12.5 Mhz.
+ * the MII MDC clock. MII MDC clock will be set to work in the range
+ * of 1.5 to 2.5Mhz
  * The output of this function is the value of MIIMCFG[MgmtClk] which
  * implicitly determines the divider value.
  * Note: the dTSEC system clock is equal to 1/2 of the FMan clock.
@@ -49,31 +50,35 @@
  * shows the relations among dtsec_freq, MgmtClk, actual divider
  * and the MII frequency:
  *
- * dtsec freq   MgmtClk     div         MII freq
- * [80..159]      0      (1/4)(1/8)   [2.5 to 5.0]
- * [160..319]     1      (1/4)(1/8)   [5.0 to 10.0]
- * [320..479]     2      (1/6)(1/8)   [6.7 to 10.0]
- * [480..639]     3      (1/8)(1/8)   [7.5 to 10.0]
- * [640..799]     4      (1/10)(1/8)  [8.0 to 10.0]
- * [800..959]     5      (1/14)(1/8)  [7.1 to 8.5]
- * [960..1119]    6      (1/20)(1/8)  [6.0 to 7.0]
- * [1120..1279]   7      (1/28)(1/8)  [5.0 to 5.7]
- * [1280..2800]   7      (1/28)(1/8)  [5.7 to 12.5]
+ * dtsec freq   MgmtClk     div        MII freq Mhz
+ * [0.....80]     1      (1/4)(1/8)    [0   to 2.5]
+ * [81...120]     2      (1/6)(1/8)    [1.6 to 2.5]
+ * [121..160]     3      (1/8)(1/8)    [1.8 to 2.5]
+ * [161..200]     4      (1/10)(1/8)   [2.0 to 2.5]
+ * [201..280]     5      (1/14)(1/8)   [1.8 to 2.5]
+ * [281..400]     6      (1/20)(1/8)   [1.1 to 2.5]
+ * [401..560]     7      (1/28)(1/8)   [1.8 to 2.5]
+ * [560..frq]     7      (1/28)(1/8)   [frq/224]
  *
  * Returns: the MIIMCFG[MgmtClk] appropriate value
  */
 
 static uint8_t dtsec_mii_get_div(uint16_t dtsec_freq)
 {
-	uint16_t mgmt_clk = (uint16_t)(dtsec_freq / 160);
+	uint16_t mgmt_clk;
 
-	if (mgmt_clk > 7)
-		mgmt_clk = 7;
+	if (dtsec_freq < 80) mgmt_clk = 1;
+	else if (dtsec_freq < 120) mgmt_clk = 2;
+	else if (dtsec_freq < 160) mgmt_clk = 3;
+	else if (dtsec_freq < 200) mgmt_clk = 4;
+	else if (dtsec_freq < 280) mgmt_clk = 5;
+	else if (dtsec_freq < 400) mgmt_clk = 6;
+	else mgmt_clk = 7;
 
 	return (uint8_t)mgmt_clk;
 }
 
-void dtsec_mii_reset(struct dtsec_mii_reg *regs)
+void fman_dtsec_mii_reset(struct dtsec_mii_reg *regs)
 {
 	/* Reset the management interface */
 	iowrite32be(ioread32be(&regs->miimcfg) | MIIMCFG_RESET_MGMT,
@@ -82,30 +87,32 @@ void dtsec_mii_reset(struct dtsec_mii_reg *regs)
 			&regs->miimcfg);
 }
 
-void dtsec_mii_init(struct dtsec_mii_reg *regs, uint16_t dtsec_freq)
-{
-	/* Setup the MII Mgmt clock speed */
-	iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
-}
 
-int dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr,
-		uint8_t reg, uint16_t data)
+int fman_dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr,
+		uint8_t reg, uint16_t data, uint16_t dtsec_freq)
 {
 	uint32_t	tmp;
 
+	/* Setup the MII Mgmt clock speed */
+	iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
+	wmb();
+
 	/* Stop the MII management read cycle */
 	iowrite32be(0, &regs->miimcom);
 	/* Dummy read to make sure MIIMCOM is written */
 	tmp = ioread32be(&regs->miimcom);
+	wmb();
 
 	/* Setting up MII Management Address Register */
 	tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
 	iowrite32be(tmp, &regs->miimadd);
+	wmb();
 
 	/* Setting up MII Management Control Register with data */
 	iowrite32be((uint32_t)data, &regs->miimcon);
 	/* Dummy read to make sure MIIMCON is written */
 	tmp = ioread32be(&regs->miimcon);
+	wmb();
 
 	/* Wait untill MII management write is complete */
 	/* todo: a timeout could be useful here */
@@ -115,19 +122,25 @@ int dtsec_mii_write_reg(struct dtsec_mii_reg *regs, uint8_t addr,
 	return 0;
 }
 
-int dtsec_mii_read_reg(struct dtsec_mii_reg *regs, uint8_t  addr,
-		uint8_t reg, uint16_t *data)
+int fman_dtsec_mii_read_reg(struct dtsec_mii_reg *regs, uint8_t  addr,
+		uint8_t reg, uint16_t *data, uint16_t dtsec_freq)
 {
 	uint32_t	tmp;
 
+	/* Setup the MII Mgmt clock speed */
+	iowrite32be((uint32_t)dtsec_mii_get_div(dtsec_freq), &regs->miimcfg);
+	wmb();
+
 	/* Setting up the MII Management Address Register */
 	tmp = (uint32_t)((addr << MIIMADD_PHY_ADDR_SHIFT) | reg);
 	iowrite32be(tmp, &regs->miimadd);
+	wmb();
 
 	/* Perform an MII management read cycle */
 	iowrite32be(MIIMCOM_READ_CYCLE, &regs->miimcom);
 	/* Dummy read to make sure MIIMCOM is written */
 	tmp = ioread32be(&regs->miimcom);
+	wmb();
 
 	/* Wait until MII management read is complete */
 	/* todo: a timeout could be useful here */
@@ -136,6 +149,7 @@ int dtsec_mii_read_reg(struct dtsec_mii_reg *regs, uint8_t  addr,
 
 	/* Read MII management status  */
 	*data = (uint16_t)ioread32be(&regs->miimstat);
+	wmb();
 
 	iowrite32be(0, &regs->miimcom);
 	/* Dummy read to make sure MIIMCOM is written */
diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fsl_fman_dtsec_mii_acc.h b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fsl_fman_dtsec_mii_acc.h
deleted file mode 100644
index 9d156c0..0000000
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/fsl_fman_dtsec_mii_acc.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2008-2012 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __FSL_FMAN_DTSEC_MII_ACC_H
-#define __FSL_FMAN_DTSEC_MII_ACC_H
-
-#include "common/general.h"
-
-
-/* MII Management Configuration Register */
-#define MIIMCFG_RESET_MGMT		0x80000000
-#define MIIMCFG_MGNTCLK_MASK		0x00000007
-#define MIIMCFG_MGNTCLK_SHIFT		0
-
-/* MII  Management Command Register */
-#define MIIMCOM_SCAN_CYCLE		0x00000002
-#define MIIMCOM_READ_CYCLE		0x00000001
-
-/* MII  Management Address Register */
-#define MIIMADD_PHY_ADDR_SHIFT		8
-#define MIIMADD_PHY_ADDR_MASK		0x00001f00
-
-#define MIIMADD_REG_ADDR_SHIFT		0
-#define MIIMADD_REG_ADDR_MASK		0x0000001f
-
-/* MII Management Indicator Register */
-#define MIIMIND_BUSY			0x00000001
-
-
-/* PHY Control Register */
-
-#define PHY_CR_PHY_RESET    0x8000
-#define PHY_CR_LOOPBACK     0x4000
-#define PHY_CR_SPEED0       0x2000
-#define PHY_CR_ANE          0x1000
-#define PHY_CR_RESET_AN     0x0200
-#define PHY_CR_FULLDUPLEX   0x0100
-#define PHY_CR_SPEED1       0x0040
-
-
-#define PHY_TBICON_SRESET   0x8000
-#define PHY_TBICON_CLK_SEL  0x0020
-
-#define PHY_TBIANA_SGMII    0x4001
-#define PHY_TBIANA_1000X    0x01a0
-
-
-/* register map */
-
-/* MII Configuration Control Memory Map Registers */
-struct dtsec_mii_reg {
-	uint32_t reserved1[72];
-	uint32_t miimcfg;	/* MII Mgmt:configuration */
-	uint32_t miimcom;	/* MII Mgmt:command       */
-	uint32_t miimadd;	/* MII Mgmt:address       */
-	uint32_t miimcon;	/* MII Mgmt:control 3     */
-	uint32_t miimstat;	/* MII Mgmt:status        */
-	uint32_t miimind;	/* MII Mgmt:indicators    */
-};
-
-/* dTSEC MII API */
-
-/* functions to access the mii registers for phy configuration.
- * this functionality may not be available for all dTSECs in the system.
- * consult the reference manual for details */
-void dtsec_mii_reset(struct dtsec_mii_reg *regs);
-/* frequency is in MHz.
- * note that dtsec clock is 1/2 of fman clock */
-void dtsec_mii_init(struct dtsec_mii_reg *regs, uint16_t dtsec_freq);
-int dtsec_mii_write_reg(struct dtsec_mii_reg *regs,
-			uint8_t addr,
-			uint8_t reg,
-			uint16_t data);
-
-int dtsec_mii_read_reg(struct dtsec_mii_reg *regs,
-			uint8_t addr,
-			uint8_t reg,
-			uint16_t *data);
-
-#endif /* __FSL_FMAN_DTSEC_MII_ACC_H */
diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/memac.c b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/memac.c
index 2687283..ca8e5da 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/memac.c
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/MAC/memac.c
@@ -415,10 +415,30 @@ static t_Error MemacSetTxPauseFrames(t_Handle h_Memac,
                                      uint16_t threshTime)
 {
     t_Memac     *p_Memac = (t_Memac *)h_Memac;
+    t_Error     err = E_OK;
 
     SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_STATE);
     SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
 
+    if (priority != 0xFF)
+    {
+        bool   PortConfigured, PreFetchEnabled;
+
+        if (FmGetTnumAgingPeriod(p_Memac->fmMacControllerDriver.h_Fm) == 0)
+            RETURN_ERROR(MAJOR, E_CONFLICT, ("For PFC operation, TNUM aging must be enabled"));
+
+        FmGetPortPreFetchConfiguration(p_Memac->fmMacControllerDriver.h_Fm,
+                                       p_Memac->fmMacControllerDriver.macId,
+                                       &PortConfigured,
+                                       &PreFetchEnabled);
+
+        if ((ENET_SPEED_FROM_MODE(p_Memac->fmMacControllerDriver.enetMode) == e_ENET_SPEED_1000) && !PortConfigured)
+            DBG(INFO, ("For PFC correct operation, prefetch must be configured on the FM Tx PORT"));
+
+        if ((ENET_SPEED_FROM_MODE(p_Memac->fmMacControllerDriver.enetMode) == e_ENET_SPEED_1000) && PortConfigured && !PreFetchEnabled)
+            DBG(WARNING, ("For PFC correct operation, prefetch must be configured on the FM Tx PORT"));
+    }
+
     fman_memac_set_tx_pause_frames(p_Memac->p_MemMap, priority, pauseTime, threshTime);
 
     return E_OK;