fmd: fmd22 integration

- Fix for PCD: key mask not properly enabled in exact match table
- Fix for PFC mapping function
- Added counters for miss entry in match and hash tables
- Added counter for IPv4 options in IP fragmentation

Change-Id: I1626afc661d412c518172d405860a33d801cd005
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/6251
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Marian-Cornel Chereji <marian.chereji@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>

Conflicts:
	drivers/net/ethernet/freescale/fman/Peripherals/FM/Port/fm_port.c
	drivers/net/ethernet/freescale/fman/Peripherals/FM/Port/fm_port.h
Change-Id: If356927d0cd4e22e8949a0106c2a403fcf1343a2
Reviewed-on: http://git.am.freescale.net:8181/7665
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>

1 files changed, 159 insertions, 406 deletions

diff --git a/drivers/net/ethernet/freescale/fman/Peripherals/FM/fm.h b/drivers/net/ethernet/freescale/fman/Peripherals/FM/fm.h
index cb97d3e..3e5b2ec 100644
--- a/drivers/net/ethernet/freescale/fman/Peripherals/FM/fm.h
+++ b/drivers/net/ethernet/freescale/fman/Peripherals/FM/fm.h
@@ -44,6 +44,7 @@
 #include "fm_ext.h"
 #include "fm_ipc.h"
 
+#include "fsl_fman.h"
 
 #define __ERR_MODULE__  MODULE_FM
 
@@ -71,6 +72,12 @@
 #define FM_EX_BMI_DISPATCH_RAM_ECC          0x00010000
 #define FM_EX_DMA_SINGLE_PORT_ECC           0x00008000
 
+#define DMA_EMSR_EMSTR_MASK                 0x0000FFFF
+
+#define DMA_THRESH_COMMQ_MASK               0xFF000000
+#define DMA_THRESH_READ_INT_BUF_MASK        0x007F0000
+#define DMA_THRESH_WRITE_INT_BUF_MASK       0x0000007F
+
 #define GET_EXCEPTION_FLAG(bitMask, exception)              \
 switch (exception){                                         \
     case e_FM_EX_DMA_BUS_ERROR:                             \
@@ -150,6 +157,146 @@ switch (exception){                                         \
         break;                                                                                      \
     }
 
+#define FMAN_EXCEPTION_TRANS(fsl_exception, _exception) \
+    switch (_exception) {\
+        case  e_FM_EX_DMA_BUS_ERROR:                    \
+            fsl_exception =  E_FMAN_EX_DMA_BUS_ERROR; break;    \
+        case  e_FM_EX_DMA_READ_ECC:                    \
+            fsl_exception =  E_FMAN_EX_DMA_READ_ECC; break;        \
+        case  e_FM_EX_DMA_SYSTEM_WRITE_ECC:                \
+            fsl_exception =  E_FMAN_EX_DMA_SYSTEM_WRITE_ECC; break;    \
+        case  e_FM_EX_DMA_FM_WRITE_ECC:                    \
+            fsl_exception =  E_FMAN_EX_DMA_FM_WRITE_ECC; break;    \
+        case  e_FM_EX_FPM_STALL_ON_TASKS:                \
+            fsl_exception =  E_FMAN_EX_FPM_STALL_ON_TASKS; break;    \
+        case  e_FM_EX_FPM_SINGLE_ECC:                    \
+            fsl_exception =  E_FMAN_EX_FPM_SINGLE_ECC; break;    \
+        case  e_FM_EX_FPM_DOUBLE_ECC:                    \
+            fsl_exception =  E_FMAN_EX_FPM_DOUBLE_ECC; break;    \
+        case  e_FM_EX_QMI_SINGLE_ECC:                    \
+            fsl_exception =  E_FMAN_EX_QMI_SINGLE_ECC; break;    \
+        case  e_FM_EX_QMI_DOUBLE_ECC:                    \
+            fsl_exception =  E_FMAN_EX_QMI_DOUBLE_ECC; break;    \
+        case  e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:            \
+            fsl_exception =  E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \
+        case  e_FM_EX_BMI_LIST_RAM_ECC:                    \
+            fsl_exception =  E_FMAN_EX_BMI_LIST_RAM_ECC; break;    \
+        case  e_FM_EX_BMI_STORAGE_PROFILE_ECC:                    \
+            fsl_exception =  E_FMAN_EX_BMI_STORAGE_PROFILE_ECC; break;    \
+        case  e_FM_EX_BMI_STATISTICS_RAM_ECC:                \
+            fsl_exception =  E_FMAN_EX_BMI_STATISTICS_RAM_ECC; break; \
+        case  e_FM_EX_BMI_DISPATCH_RAM_ECC:                \
+            fsl_exception =  E_FMAN_EX_BMI_DISPATCH_RAM_ECC; break;    \
+        case  e_FM_EX_IRAM_ECC:                        \
+            fsl_exception =  E_FMAN_EX_IRAM_ECC; break;        \
+        case  e_FM_EX_MURAM_ECC:                    \
+            fsl_exception =  E_FMAN_EX_MURAM_ECC; break;        \
+        default: \
+            fsl_exception =  E_FMAN_EX_DMA_BUS_ERROR; break;    \
+    }
+
+#define FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, _cache_override) \
+    switch (_cache_override){ \
+        case  e_FM_DMA_NO_CACHE_OR:                    \
+            fsl_cache_override =  E_FMAN_DMA_NO_CACHE_OR; break;    \
+        case  e_FM_DMA_NO_STASH_DATA:                    \
+            fsl_cache_override =  E_FMAN_DMA_NO_STASH_DATA; break;        \
+        case  e_FM_DMA_MAY_STASH_DATA:                    \
+            fsl_cache_override =  E_FMAN_DMA_MAY_STASH_DATA; break;    \
+        case  e_FM_DMA_STASH_DATA:                        \
+            fsl_cache_override =  E_FMAN_DMA_STASH_DATA; break;        \
+        default: \
+            fsl_cache_override =  E_FMAN_DMA_NO_CACHE_OR; break;    \
+    }
+
+#define FMAN_AID_MODE_TRANS(fsl_aid_mode, _aid_mode) \
+    switch (_aid_mode){ \
+        case  e_FM_DMA_AID_OUT_PORT_ID:                    \
+            fsl_aid_mode =  E_FMAN_DMA_AID_OUT_PORT_ID; break;    \
+        case  e_FM_DMA_AID_OUT_TNUM:                    \
+            fsl_aid_mode =  E_FMAN_DMA_AID_OUT_TNUM; break;        \
+        default: \
+            fsl_aid_mode =  E_FMAN_DMA_AID_OUT_PORT_ID; break;    \
+    }
+
+#define FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, _dma_dbg_cnt) \
+    switch (_dma_dbg_cnt){ \
+        case  e_FM_DMA_DBG_NO_CNT:                    \
+            fsl_dma_dbg_cnt =  E_FMAN_DMA_DBG_NO_CNT; break;    \
+        case  e_FM_DMA_DBG_CNT_DONE:                    \
+            fsl_dma_dbg_cnt =  E_FMAN_DMA_DBG_CNT_DONE; break;        \
+        case  e_FM_DMA_DBG_CNT_COMM_Q_EM:                    \
+            fsl_dma_dbg_cnt =  E_FMAN_DMA_DBG_CNT_COMM_Q_EM; break;    \
+        case  e_FM_DMA_DBG_CNT_INT_READ_EM:                        \
+            fsl_dma_dbg_cnt =  E_FMAN_DMA_DBG_CNT_INT_READ_EM; break;        \
+        case  e_FM_DMA_DBG_CNT_INT_WRITE_EM:                        \
+            fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_WRITE_EM ; break;        \
+        case  e_FM_DMA_DBG_CNT_FPM_WAIT:                        \
+            fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_FPM_WAIT ; break;        \
+        case  e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC:                        \
+            fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC ; break;        \
+        case  e_FM_DMA_DBG_CNT_RAW_WAR_PROT:                        \
+            fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT ; break;        \
+        default: \
+            fsl_dma_dbg_cnt =  E_FMAN_DMA_DBG_NO_CNT; break;    \
+    }
+
+#define FMAN_DMA_EMER_TRANS(fsl_dma_emer, _dma_emer) \
+    switch (_dma_emer){ \
+        case  e_FM_DMA_EM_EBS:                    \
+            fsl_dma_emer =  E_FMAN_DMA_EM_EBS; break;    \
+        case  e_FM_DMA_EM_SOS:                    \
+            fsl_dma_emer =  E_FMAN_DMA_EM_SOS; break;        \
+        default: \
+            fsl_dma_emer =  E_FMAN_DMA_EM_EBS; break;    \
+    }
+
+#define FMAN_DMA_ERR_TRANS(fsl_dma_err, _dma_err) \
+    switch (_dma_err){ \
+        case  e_FM_DMA_ERR_CATASTROPHIC:                    \
+            fsl_dma_err =  E_FMAN_DMA_ERR_CATASTROPHIC; break;    \
+        case  e_FM_DMA_ERR_REPORT:                    \
+            fsl_dma_err =  E_FMAN_DMA_ERR_REPORT; break;        \
+        default: \
+            fsl_dma_err =  E_FMAN_DMA_ERR_CATASTROPHIC; break;    \
+    }
+
+#define FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, _catastrophic_err) \
+    switch (_catastrophic_err){ \
+        case  e_FM_CATASTROPHIC_ERR_STALL_PORT:                    \
+            fsl_catastrophic_err =  E_FMAN_CATAST_ERR_STALL_PORT; break;    \
+        case  e_FM_CATASTROPHIC_ERR_STALL_TASK:                    \
+            fsl_catastrophic_err =  E_FMAN_CATAST_ERR_STALL_TASK; break;        \
+        default: \
+            fsl_catastrophic_err =  E_FMAN_CATAST_ERR_STALL_PORT; break;    \
+    }
+
+#define FMAN_COUNTERS_TRANS(fsl_counters, _counters) \
+    switch (_counters){ \
+        case  e_FM_COUNTERS_ENQ_TOTAL_FRAME:                    \
+            fsl_counters =  E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break;    \
+        case  e_FM_COUNTERS_DEQ_TOTAL_FRAME:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_TOTAL_FRAME; break;        \
+        case  e_FM_COUNTERS_DEQ_0:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_0; break;    \
+        case  e_FM_COUNTERS_DEQ_1:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_1; break;        \
+        case  e_FM_COUNTERS_DEQ_2:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_2; break;    \
+        case  e_FM_COUNTERS_DEQ_3:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_3; break;        \
+        case  e_FM_COUNTERS_DEQ_FROM_DEFAULT:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_FROM_DEFAULT; break;    \
+        case  e_FM_COUNTERS_DEQ_FROM_CONTEXT:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_FROM_CONTEXT; break;        \
+        case  e_FM_COUNTERS_DEQ_FROM_FD:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_FROM_FD; break;    \
+        case  e_FM_COUNTERS_DEQ_CONFIRM:                    \
+            fsl_counters =  E_FMAN_COUNTERS_DEQ_CONFIRM; break;        \
+        default: \
+            fsl_counters =  E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break;    \
+    }
+
 /**************************************************************************//**
  @Description       defaults
 *//***************************************************************************/
@@ -191,7 +338,6 @@ switch (exception){                                         \
 #define DEFAULT_haltOnUnrecoverableEccError FALSE   /* do not change! if changed, must be disabled for rev1 ! */
 #define DEFAULT_externalEccRamsEnable       FALSE
 #define DEFAULT_VerifyUcode                 FALSE
-#define DEFAULT_tnumAgingPeriod             0
 
 #if (DPAA_VERSION < 11)
 #define DEFAULT_totalFifoSize(major)    \
@@ -248,7 +394,6 @@ switch (exception){                                         \
 #define DEFAULT_fmCtl2DispTh                16
 #endif /* (DPAA_VERSION < 11) */
 
-
 #define FM_TIMESTAMP_1_USEC_BIT             8
 
 /**************************************************************************//**
@@ -316,7 +461,6 @@ switch (exception){                                         \
 #define FM_MM_SP                0x000dc000
 #endif /* (DPAA_VERSION >= 11) */
 
-
 /**************************************************************************//**
  @Description       Memory Mapped Registers
 *//***************************************************************************/
@@ -324,145 +468,6 @@ switch (exception){                                         \
 #if defined(__MWERKS__) && !defined(__GNUC__)
 #pragma pack(push,1)
 #endif /* defined(__MWERKS__) && ... */
-
-typedef _Packed struct
-{
-    volatile uint32_t   fmfp_tnc;       /**< FPM TNUM Control */
-    volatile uint32_t   fmfp_prc;       /**< FPM Port_ID FmCtl Association */
-    volatile uint32_t   fmfp_brkc;      /**< FPM Breakpoint Control */
-    volatile uint32_t   fmfp_mxd;       /**< FPM Maximum dispatch */
-    volatile uint32_t   fmfp_dis1;      /**< FPM Dispatch Thresholds1 */
-    volatile uint32_t   fmfp_dis2;      /**< FPM Dispatch Thresholds2  */
-    volatile uint32_t   fm_epi;         /**< FM Error Pending Interrupts */
-    volatile uint32_t   fm_rie;         /**< FM Error Interrupt Enable */
-    volatile uint32_t   fmfp_fcev[4];   /**< FPM FMan-Controller Event 1-4 */
-    volatile uint8_t    res1[16];       /**< reserved */
-    volatile uint32_t   fmfp_cee[4];    /**< PM FMan-Controller Event 1-4 */
-    volatile uint8_t    res2[16];       /**< reserved */
-    volatile uint32_t   fmfp_tsc1;      /**< FPM TimeStamp Control1 */
-    volatile uint32_t   fmfp_tsc2;      /**< FPM TimeStamp Control2 */
-    volatile uint32_t   fmfp_tsp;       /**< FPM Time Stamp */
-    volatile uint32_t   fmfp_tsf;       /**< FPM Time Stamp Fraction */
-    volatile uint32_t   fm_rcr;         /**< FM Rams Control */
-    volatile uint32_t   fmfp_extc;      /**< FPM External Requests Control */
-    volatile uint32_t   fmfp_ext1;      /**< FPM External Requests Config1 */
-    volatile uint32_t   fmfp_ext2;      /**< FPM External Requests Config2 */
-    volatile uint32_t   fmfp_drd[4];    /**< FPM Data_Ram Data 0-3 */
-    volatile uint8_t    res3[48];       /**< reserved */
-    volatile uint32_t   fmfp_dra;       /**< FPM Data Ram Access */
-    volatile uint32_t   fm_ip_rev_1;    /**< FM IP Block Revision 1 */
-    volatile uint32_t   fm_ip_rev_2;    /**< FM IP Block Revision 2 */
-    volatile uint32_t   fm_rstc;        /**< FM Reset Command */
-    volatile uint32_t   fm_cld;         /**< FM Classifier Debug */
-    volatile uint32_t   fm_npi;         /**< FM Normal Pending Interrupts  */
-    volatile uint32_t   fmfp_exte;      /**< FPM External Requests Enable */
-    volatile uint32_t   fmfp_ee;        /**< FPM Event & Enable */
-    volatile uint32_t   fmfp_cev[4];    /**< FPM CPU Event 1-4 */
-    volatile uint8_t    res4[16];       /**< reserved */
-    volatile uint32_t   fmfp_ps[0x40];  /**< FPM Port Status */
-    volatile uint8_t    reserved1[0x200];
-    volatile uint32_t   fmfp_ts[128];     /**< 0x400: FPM Task Status */
-} _PackedType t_FmFpmRegs;
-
-#define NUM_OF_DBG_TRAPS    3
-
-typedef _Packed struct
-{
-   volatile uint32_t   fmbm_init;       /**< BMI Initialization */
-   volatile uint32_t   fmbm_cfg1;       /**< BMI Configuration 1 */
-   volatile uint32_t   fmbm_cfg2;       /**< BMI Configuration 2 */
-   volatile uint32_t   reserved[5];
-   volatile uint32_t   fmbm_ievr;       /**< Interrupt Event Register */
-   volatile uint32_t   fmbm_ier;        /**< Interrupt Enable Register */
-   volatile uint32_t   fmbm_ifr;        /**< Interrupt Force Register */
-   volatile uint32_t   reserved1[5];
-   volatile uint32_t   fmbm_arb[8];     /**< BMI Arbitration */
-   volatile uint32_t   reserved2[12];
-   volatile uint32_t   fmbm_dtc[NUM_OF_DBG_TRAPS];      /**< BMI Debug Trap Counter */
-   volatile uint32_t   reserved3;
-   volatile uint32_t   fmbm_dcv[NUM_OF_DBG_TRAPS][4];   /**< BMI Debug Compare Value */
-   volatile uint32_t   fmbm_dcm[NUM_OF_DBG_TRAPS][4];   /**< BMI Debug Compare Mask */
-   volatile uint32_t   fmbm_gde;        /**< BMI Global Debug Enable */
-   volatile uint32_t   fmbm_pp[63];     /**< BMI Port Parameters */
-   volatile uint32_t   reserved4;
-   volatile uint32_t   fmbm_pfs[63];    /**< BMI Port FIFO Size */
-   volatile uint32_t   reserved5;
-   volatile uint32_t   fmbm_spliodn[63];   /**< Port Partition ID */
-} _PackedType t_FmBmiRegs;
-
-typedef _Packed struct
-{
-    volatile uint32_t   fmqm_gc;        /**<  General Configuration Register */
-    volatile uint32_t   reserved0;
-    volatile uint32_t   fmqm_eie;       /**<  Error Interrupt Event Register */
-    volatile uint32_t   fmqm_eien;      /**<  Error Interrupt Enable Register */
-    volatile uint32_t   fmqm_eif;       /**<  Error Interrupt Force Register */
-    volatile uint32_t   fmqm_ie;        /**<  Interrupt Event Register */
-    volatile uint32_t   fmqm_ien;       /**<  Interrupt Enable Register */
-    volatile uint32_t   fmqm_if;        /**<  Interrupt Force Register */
-    volatile uint32_t   fmqm_gs;        /**<  Global Status Register */
-    volatile uint32_t   reserved1;
-    volatile uint32_t   fmqm_etfc;      /**<  Enqueue Total Frame Counter */
-    volatile uint32_t   fmqm_dtfc;      /**<  Dequeue Total Frame Counter */
-    volatile uint32_t   fmqm_dc0;       /**<  Dequeue Counter 0 */
-    volatile uint32_t   fmqm_dc1;       /**<  Dequeue Counter 1 */
-    volatile uint32_t   fmqm_dc2;       /**<  Dequeue Counter 2 */
-    volatile uint32_t   fmqm_dc3;       /**<  Dequeue Counter 3 */
-    volatile uint32_t   fmqm_dfdc;      /**<  Dequeue FQID from Default Counter */
-    volatile uint32_t   fmqm_dfcc;      /**<  Dequeue FQID from Context Counter */
-    volatile uint32_t   fmqm_dffc;      /**<  Dequeue FQID from FD Counter */
-    volatile uint32_t   fmqm_dcc;       /**<  Dequeue Confirm Counter */
-    volatile uint32_t   reserved1a[7];
-    volatile uint32_t   fmqm_tapc;      /**<  Tnum Aging Period Control */
-    volatile uint32_t   fmqm_dmcvc;     /**<  Dequeue MAC Command Valid Counter */
-    volatile uint32_t   fmqm_difdcc;    /**<  Dequeue Invalid FD Command Counter */
-    volatile uint32_t   fmqm_da1v;      /**<  Dequeue A1 Valid Counter */
-    volatile uint32_t   reserved1b;
-    volatile uint32_t   fmqm_dtc;       /**<  0x0080 Debug Trap Counter */
-    volatile uint32_t   fmqm_efddd;     /**<  0x0084 Enqueue Frame Descriptor Dynamic Debug */
-    volatile uint32_t   reserved3[2];
-    _Packed struct {
-        volatile uint32_t   fmqm_dtcfg1;    /**<  0x0090 Debug Trap Configuration 1 Register */
-        volatile uint32_t   fmqm_dtval1;    /**<  Debug Trap Value 1 Register */
-        volatile uint32_t   fmqm_dtm1;      /**<  Debug Trap Mask 1 Register */
-        volatile uint32_t   fmqm_dtc1;      /**<  Debug Trap Counter 1 Register */
-        volatile uint32_t   fmqm_dtcfg2;    /**<  Debug Trap Configuration 2 Register */
-        volatile uint32_t   fmqm_dtval2;    /**<  Debug Trap Value 2 Register */
-        volatile uint32_t   fmqm_dtm2;      /**<  Debug Trap Mask 2 Register */
-        volatile uint32_t   reserved1;
-    } _PackedType dbgTraps[NUM_OF_DBG_TRAPS];
-} _PackedType t_FmQmiRegs;
-
-typedef _Packed struct
-{
-    volatile uint32_t   fmdmsr;         /**< FM DMA status register 0x04 */
-    volatile uint32_t   fmdmmr;         /**< FM DMA mode register 0x08 */
-    volatile uint32_t   fmdmtr;         /**< FM DMA bus threshold register 0x0c */
-    volatile uint32_t   fmdmhy;         /**< FM DMA bus hysteresis register 0x10 */
-    volatile uint32_t   fmdmsetr;       /**< FM DMA SOS emergency Threshold Register 0x14 */
-    volatile uint32_t   fmdmtah;        /**< FM DMA transfer bus address high register 0x18  */
-    volatile uint32_t   fmdmtal;        /**< FM DMA transfer bus address low register 0x1C  */
-    volatile uint32_t   fmdmtcid;       /**< FM DMA transfer bus communication ID register 0x20  */
-    volatile uint32_t   fmdmra;         /**< FM DMA bus internal ram address register 0x24  */
-    volatile uint32_t   fmdmrd;         /**< FM DMA bus internal ram data register 0x28  */
-    volatile uint32_t   fmdmwcr;        /**< FM DMA CAM watchdog counter value 0x2C  */
-    volatile uint32_t   fmdmebcr;       /**< FM DMA CAM base in MURAM register 0x30  */
-    volatile uint32_t   fmdmccqdr;      /**< FM DMA CAM and CMD Queue Debug register 0x34  */
-    volatile uint32_t   fmdmccqvr1;     /**< FM DMA CAM and CMD Queue Value register #1 0x38  */
-    volatile uint32_t   fmdmccqvr2;     /**< FM DMA CAM and CMD Queue Value register #2 0x3C  */
-    volatile uint32_t   fmdmcqvr3;      /**< FM DMA CMD Queue Value register #3 0x40  */
-    volatile uint32_t   fmdmcqvr4;      /**< FM DMA CMD Queue Value register #4 0x44  */
-    volatile uint32_t   fmdmcqvr5;      /**< FM DMA CMD Queue Value register #5 0x48  */
-    volatile uint32_t   fmdmsefrc;      /**< FM DMA Semaphore Entry Full Reject Counter 0x50  */
-    volatile uint32_t   fmdmsqfrc;      /**< FM DMA Semaphore Queue Full Reject Counter 0x54  */
-    volatile uint32_t   fmdmssrc;       /**< FM DMA Semaphore SYNC Reject Counter 0x54  */
-    volatile uint32_t   fmdmdcr;        /**< FM DMA Debug Counter */
-    volatile uint32_t   fmdmemsr;       /**< FM DMA Emrgency Smoother Register */
-    volatile uint32_t   reserved;
-    volatile uint32_t   fmdmplr[FM_MAX_NUM_OF_HW_PORT_IDS/2];
-                                        /**< FM DMA PID-LIODN # register  */
-} _PackedType t_FmDmaRegs;
-
 typedef _Packed struct
 {
     volatile uint32_t   iadd;           /**< FM IRAM instruction address register */
@@ -506,8 +511,6 @@ typedef _Packed struct t_FmTrbRegs
 #if defined(__MWERKS__) && !defined(__GNUC__)
 #pragma pack(pop)
 #endif /* defined(__MWERKS__) && ... */
-
-
 /**************************************************************************//**
  @Description       General defines
 *//***************************************************************************/
@@ -515,192 +518,10 @@ typedef _Packed struct t_FmTrbRegs
 #define FM_FW_DEBUG_INSTRUCTION             0x6ffff805UL
 
 /**************************************************************************//**
- @Description       DMA definitions
-*//***************************************************************************/
-/* masks */
-#define DMA_MODE_AID_OR                     0x20000000
-#define DMA_MODE_SBER                       0x10000000
-#define DMA_MODE_BER                        0x00200000
-#define DMA_MODE_EB                         0x00100000
-#define DMA_MODE_ECC                        0x00000020
-#define DMA_MODE_PRIVILEGE_PROT             0x00001000
-#define DMA_MODE_SECURE_PROT                0x00000800
-#define DMA_MODE_EMERGENCY_READ             0x00080000
-#define DMA_MODE_EMERGENCY_WRITE            0x00040000
-#define DMA_MODE_CACHE_OR_MASK              0xC0000000
-#define DMA_MODE_CEN_MASK                   0x0000E000
-#define DMA_MODE_DBG_MASK                   0x00000380
-
-#define DMA_TRANSFER_PORTID_MASK            0xFF000000
-#define DMA_TRANSFER_TNUM_MASK              0x00FF0000
-#define DMA_TRANSFER_LIODN_MASK             0x00000FFF
-
-#define DMA_HIGH_LIODN_MASK                 0x0FFF0000
-#define DMA_LOW_LIODN_MASK                  0x00000FFF
-
-#define DMA_STATUS_CMD_QUEUE_NOT_EMPTY      0x10000000
-#define DMA_STATUS_BUS_ERR                  0x08000000
-#define DMA_STATUS_READ_ECC                 0x04000000
-#define DMA_STATUS_SYSTEM_WRITE_ECC         0x02000000
-#define DMA_STATUS_FM_WRITE_ECC             0x01000000
-#define DMA_STATUS_SYSTEM_DPEXT_ECC         0x00800000
-#define DMA_STATUS_FM_DPEXT_ECC             0x00400000
-#define DMA_STATUS_SYSTEM_DPDAT_ECC         0x00200000
-#define DMA_STATUS_FM_DPDAT_ECC             0x00100000
-#define DMA_STATUS_FM_SPDAT_ECC             0x00080000
-
-#define DMA_STATUS_FM_ECC                   (DMA_STATUS_READ_ECC |          \
-                                             DMA_STATUS_SYSTEM_WRITE_ECC |  \
-                                             DMA_STATUS_FM_WRITE_ECC |      \
-                                             DMA_STATUS_SYSTEM_DPEXT_ECC |  \
-                                             DMA_STATUS_FM_DPEXT_ECC |      \
-                                             DMA_STATUS_SYSTEM_DPDAT_ECC |  \
-                                             DMA_STATUS_FM_DPDAT_ECC |      \
-                                             DMA_STATUS_FM_SPDAT_ECC)
-
-#define FM_LIODN_BASE_MASK                  0x00000FFF
-
-#define DMA_EMSR_EMSTR_MASK                 0x0000FFFF
-
-#define DMA_THRESH_COMMQ_MASK               0xFF000000
-#define DMA_THRESH_READ_INT_BUF_MASK        0x007F0000
-#define DMA_THRESH_WRITE_INT_BUF_MASK       0x0000007F
-
-/* shifts */
-#define DMA_MODE_CACHE_OR_SHIFT             30
-#define DMA_MODE_BUS_PRI_SHIFT              16
-#define DMA_MODE_AXI_DBG_SHIFT              24
-#define DMA_MODE_CEN_SHIFT                  13
-#define DMA_MODE_BUS_PROT_SHIFT             10
-#define DMA_MODE_DBG_SHIFT                  7
-#define DMA_MODE_EMERGENCY_LEVEL_SHIFT      6
-#define DMA_MODE_AID_MODE_SHIFT             4
-#define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS   16
-#define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES     64
-
-#define DMA_THRESH_COMMQ_SHIFT              24
-#define DMA_THRESH_READ_INT_BUF_SHIFT       16
-
-#define DMA_LIODN_SHIFT                     16
-
-#define DMA_TRANSFER_PORTID_SHIFT           24
-#define DMA_TRANSFER_TNUM_SHIFT             16
-
-/* sizes */
-#define DMA_MAX_WATCHDOG                    0xffffffff
-
-/* others */
-#define DMA_CAM_SIZEOF_ENTRY                0x40
-#define DMA_CAM_ALIGN                       0x1000
-#define DMA_CAM_UNITS                       8
-
-
-/**************************************************************************//**
  @Description       FPM defines
 *//***************************************************************************/
 /* masks */
-#define FPM_EV_MASK_DOUBLE_ECC          0x80000000
-#define FPM_EV_MASK_STALL               0x40000000
-#define FPM_EV_MASK_SINGLE_ECC          0x20000000
-#define FPM_EV_MASK_RELEASE_FM          0x00010000
-#define FPM_EV_MASK_DOUBLE_ECC_EN       0x00008000
-#define FPM_EV_MASK_STALL_EN            0x00004000
-#define FPM_EV_MASK_SINGLE_ECC_EN       0x00002000
-#define FPM_EV_MASK_EXTERNAL_HALT       0x00000008
-#define FPM_EV_MASK_ECC_ERR_HALT        0x00000004
-
-#define FPM_RAM_CTL_RAMS_ECC_EN         0x80000000
-#define FPM_RAM_CTL_IRAM_ECC_EN         0x40000000
-#define FPM_RAM_CTL_MURAM_ECC           0x00008000
-#define FPM_RAM_CTL_IRAM_ECC            0x00004000
-#define FPM_RAM_CTL_MURAM_TEST_ECC      0x20000000
-#define FPM_RAM_CTL_IRAM_TEST_ECC       0x10000000
-#define FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL 0x08000000
-
-#define FPM_IRAM_ECC_ERR_EX_EN          0x00020000
-#define FPM_MURAM_ECC_ERR_EX_EN         0x00040000
-
-#define FPM_REV1_MAJOR_MASK             0x0000FF00
-#define FPM_REV1_MINOR_MASK             0x000000FF
-
-#define FPM_REV2_INTEG_MASK             0x00FF0000
-#define FPM_REV2_ERR_MASK               0x0000FF00
-#define FPM_REV2_CFG_MASK               0x000000FF
-
-#define FPM_TS_FRACTION_MASK            0x0000FFFF
-#define FPM_TS_CTL_EN                   0x80000000
-
-#define FPM_PRC_REALSE_STALLED          0x00800000
-
-#define FPM_PS_STALLED                  0x00800000
-#define FPM_PS_FM_CTL1_SEL              0x80000000
-#define FPM_PS_FM_CTL2_SEL              0x40000000
-#define FPM_PS_FM_CTL_SEL_MASK          (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL)
-
-#define FPM_RSTC_FM_RESET               0x80000000
-#define FPM_RSTC_1G0_RESET              0x40000000
-#define FPM_RSTC_1G1_RESET              0x20000000
-#define FPM_RSTC_1G2_RESET              0x10000000
-#define FPM_RSTC_1G3_RESET              0x08000000
-#define FPM_RSTC_10G0_RESET             0x04000000
-#define FPM_RSTC_1G4_RESET              0x02000000
-#define FPM_RSTC_1G5_RESET              0x01000000
-#define FPM_RSTC_1G6_RESET              0x00800000
-#define FPM_RSTC_1G7_RESET              0x00400000
-#define FPM_RSTC_10G1_RESET             0x00200000
-
-
-#define FPM_DISP_LIMIT_MASK             0x1F000000
-#define FPM_THR1_PRS_MASK               0xFF000000
-#define FPM_THR1_KG_MASK                0x00FF0000
-#define FPM_THR1_PLCR_MASK              0x0000FF00
-#define FPM_THR1_BMI_MASK               0x000000FF
-
-#define FPM_THR2_QMI_ENQ_MASK           0xFF000000
-#define FPM_THR2_QMI_DEQ_MASK           0x000000FF
-#define FPM_THR2_FM_CTL1_MASK           0x00FF0000
-#define FPM_THR2_FM_CTL2_MASK           0x0000FF00
-
 #define FPM_BRKC_RDBG                   0x00000200
-
-/* shifts */
-#define FPM_DISP_LIMIT_SHIFT            24
-
-#define FPM_THR1_PRS_SHIFT              24
-#define FPM_THR1_KG_SHIFT               16
-#define FPM_THR1_PLCR_SHIFT             8
-#define FPM_THR1_BMI_SHIFT              0
-
-#define FPM_THR2_QMI_ENQ_SHIFT          24
-#define FPM_THR2_QMI_DEQ_SHIFT          0
-#define FPM_THR2_FM_CTL1_SHIFT          16
-#define FPM_THR2_FM_CTL2_SHIFT          8
-
-#define FPM_EV_MASK_CAT_ERR_SHIFT       1
-#define FPM_EV_MASK_DMA_ERR_SHIFT       0
-
-#define FPM_REV1_MAJOR_SHIFT            8
-#define FPM_REV1_MINOR_SHIFT            0
-
-#define FPM_REV2_INTEG_SHIFT            16
-#define FPM_REV2_ERR_SHIFT              8
-#define FPM_REV2_CFG_SHIFT              0
-
-#define FPM_TS_INT_SHIFT                16
-
-#define FPM_PORT_FM_CTL_PORTID_SHIFT      24
-
-#define FPM_PS_FM_CTL_SEL_SHIFT           30
-#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT      16
-
-/* Interrupts defines */
-#define FPM_EVENT_FM_CTL_0                0x00008000
-#define FPM_EVENT_FM_CTL                  0x0000FF00
-#define FPM_EVENT_FM_CTL_BRK              0x00000080
-
-/* others */
-#define FPM_MAX_DISP_LIMIT              31
-
 /**************************************************************************//**
  @Description       BMI defines
 *//***************************************************************************/
@@ -710,52 +531,14 @@ typedef _Packed struct t_FmTrbRegs
 #define BMI_ERR_INTR_EN_LIST_RAM_ECC        0x40000000
 #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC  0x20000000
 #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC    0x10000000
-
-#define BMI_NUM_OF_TASKS_MASK               0x3F000000 /* port */
-#define BMI_NUM_OF_EXTRA_TASKS_MASK         0x000F0000
-#define BMI_NUM_OF_DMAS_MASK                0x00000F00
-#define BMI_NUM_OF_EXTRA_DMAS_MASK          0x0000000F
-#define BMI_FIFO_SIZE_MASK                  0x000003FF /* port */
-#define BMI_EXTRA_FIFO_SIZE_MASK            0x03FF0000
-#define BMI_CFG2_DMAS_MASK                  0x0000003F
-
-#define BMI_TOTAL_FIFO_SIZE_MASK           0x07FF0000
-#define BMI_TOTAL_NUM_OF_TASKS_MASK        0x007F0000
-/* shifts */
-#define BMI_CFG2_TASKS_SHIFT            16
-#define BMI_CFG2_DMAS_SHIFT             0
-#define BMI_CFG1_FIFO_SIZE_SHIFT        16
-#define BMI_FIFO_SIZE_SHIFT             0
-#define BMI_EXTRA_FIFO_SIZE_SHIFT       16
-#define BMI_NUM_OF_TASKS_SHIFT          24
-#define BMI_EXTRA_NUM_OF_TASKS_SHIFT    16
-#define BMI_NUM_OF_DMAS_SHIFT           8
-#define BMI_EXTRA_NUM_OF_DMAS_SHIFT     0
-
-/* others */
-#define BMI_FIFO_ALIGN                  0x100
-
 /**************************************************************************//**
  @Description       QMI defines
 *//***************************************************************************/
 /* masks */
-#define QMI_CFG_ENQ_EN                  0x80000000
-#define QMI_CFG_DEQ_EN                  0x40000000
-#define QMI_CFG_EN_COUNTERS             0x10000000
-#define QMI_CFG_SOFT_RESET              0x01000000
-#define QMI_CFG_DEQ_MASK                0x0000003F
-#define QMI_CFG_ENQ_MASK                0x00003F00
-
-#define QMI_GS_HALT_NOT_BUSY            0x00000002
-
 #define QMI_ERR_INTR_EN_DOUBLE_ECC      0x80000000
 #define QMI_ERR_INTR_EN_DEQ_FROM_DEF    0x40000000
 #define QMI_INTR_EN_SINGLE_ECC          0x80000000
 
-/* shifts */
-#define QMI_CFG_ENQ_SHIFT               8
-#define QMI_TAPC_TAP                    22
-
 /**************************************************************************//**
  @Description       IRAM defines
 *//***************************************************************************/
@@ -772,44 +555,11 @@ typedef _Packed struct t_FmTrbRegs
 #define TRB_TCRH_DISABLE_COUNTERS   0x8400C000
 #define TRB_TCRL_RESET              0x20000000
 #define TRB_TCRL_UTIL               0x00000460
-
 typedef struct {
     void        (*f_Isr) (t_Handle h_Arg, uint32_t event);
     t_Handle    h_SrcHandle;
 } t_FmanCtrlIntrSrc;
 
-typedef struct
-{
- /*   uint8_t                     numOfPartitions; */
-    bool                        resetOnInit;
-    t_FmThresholds              thresholds;
-    e_FmDmaCacheOverride        dmaCacheOverride;
-    e_FmDmaAidMode              dmaAidMode;
-    bool                        dmaAidOverride;
-    uint8_t                     dmaAxiDbgNumOfBeats;
-    uint8_t                     dmaCamNumOfEntries;
-    uint32_t                    dmaWatchdog;
-    t_FmDmaThresholds           dmaCommQThresholds;
-    t_FmDmaThresholds           dmaWriteBufThresholds;
-    t_FmDmaThresholds           dmaReadBufThresholds;
-    uint32_t                    dmaSosEmergency;
-    e_FmDmaDbgCntMode           dmaDbgCntMode;
-    bool                        dmaStopOnBusError;
-    bool                        dmaEnEmergency;
-    t_FmDmaEmergency            dmaEmergency;
-    bool                        dmaEnEmergencySmoother;
-    uint32_t                    dmaEmergencySwitchCounter;
-    bool                        haltOnExternalActivation;
-    bool                        haltOnUnrecoverableEccError;
-    e_FmCatastrophicErr         catastrophicErr;
-    e_FmDmaErr                  dmaErr;
-    bool                        enMuramTestMode;
-    bool                        enIramTestMode;
-    bool                        externalEccRamsEnable;
-    t_FmFirmwareParams          firmware;
-    bool                        fwVerify;
-    uint32_t                    userSetExceptions;
-} t_FmDriverParam;
 
 typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event);
 
@@ -817,6 +567,7 @@ typedef struct
 {
 /***************************/
 /* Master/Guest parameters */
+/***************************/
     uint8_t                     fmId;
     e_FmPortType                portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS];
     uint16_t                    fmClkFreq;
@@ -877,10 +628,8 @@ typedef struct t_FmSp {
     t_FmPcdSpEntry  profiles[FM_VSP_MAX_NUM_OF_ENTRIES];
     t_FmMapParam    portsMapping[FM_MAX_NUM_OF_PORTS];
 } t_FmSp;
-
 #endif /* (DPAA_VERSION >= 11) */
 
-
 typedef struct t_Fm
 {
 /***************************/
@@ -900,10 +649,11 @@ typedef struct t_Fm
 /* Master Only parameters */
 /**************************/
 /* locals for recovery */
-    t_FmFpmRegs                 *p_FmFpmRegs;
-    t_FmBmiRegs                 *p_FmBmiRegs;
-    t_FmQmiRegs                 *p_FmQmiRegs;
-    t_FmDmaRegs                 *p_FmDmaRegs;
+    struct fman_fpm_regs *p_FmFpmRegs;
+    struct fman_bmi_regs *p_FmBmiRegs;
+    struct fman_qmi_regs *p_FmQmiRegs;
+    struct fman_dma_regs *p_FmDmaRegs;
+    struct fman_regs            *p_FmRegs;
     t_FmExceptionsCallback      *f_Exception;
     t_FmBusErrorCallback        *f_BusError;
     t_Handle                    h_App;                          /* Application handle */
@@ -918,9 +668,10 @@ typedef struct t_Fm
     uintptr_t                   vspBaseAddr;
 #endif /* (DPAA_VERSION >= 11) */
     bool                        portsPreFetchConfigured[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
-    bool                        portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS];      /* Prefetch value per Tx-port */
+    bool                        portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS];      /* Prefetch configration per Tx-port */
 
 /* un-needed for recovery */
+    struct fman_cfg             *p_FmDriverParam;
     t_Handle                    h_FmMuram;
     uint64_t                    fmMuramPhysBaseAddr;
     bool                        independentMode;
@@ -930,8 +681,10 @@ typedef struct t_Fm
     uintptr_t                   fifoBaseAddr;                   /* save for freeing */
     t_FmanCtrlIntrSrc           fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];    /* FM exceptions user callback */
     bool                        usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];
-
-    t_FmDriverParam             *p_FmDriverParam;
+    t_FmFirmwareParams          firmware;
+    bool                        fwVerify;
+    bool                        resetOnInit;
+    uint32_t                    userSetExceptions;
 } t_Fm;