diff options
| author | Michael Buesch <mb@bu3sch.de> | 2008-01-09 17:39:09 (GMT) |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-01-28 23:09:32 (GMT) |
| commit | 5250703e3144e50fbeceb4d1fc01ea2fd159fd4a (patch) | |
| tree | b3512b57ba5cfee3f838f87697f428931a098771 /drivers/net/wireless/b43/phy.h | |
| parent | 424047e6c684bef2872bd7af7d0e3961c6503981 (diff) | |
| download | linux-fsl-qoriq-5250703e3144e50fbeceb4d1fc01ea2fd159fd4a.tar.xz | |
b43: Fix PHY register routing
This fixes the PHY routing bit handling.
This is needed for N-PHY.
No functional change to A-PHY and G-PHY code.
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43/phy.h')
| -rw-r--r-- | drivers/net/wireless/b43/phy.h | 44 |
1 files changed, 24 insertions, 20 deletions
diff --git a/drivers/net/wireless/b43/phy.h b/drivers/net/wireless/b43/phy.h index 5d09fb1..4ee01d5 100644 --- a/drivers/net/wireless/b43/phy.h +++ b/drivers/net/wireless/b43/phy.h @@ -9,17 +9,21 @@ struct b43_phy; /*** PHY Registers ***/ /* Routing */ -#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */ -#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */ -#define B43_PHYROUTE_N_BMODE 0x3000 /* N-PHY BMODE registers */ - -/* Base registers. */ -#define B43_PHY_BASE(reg) (reg) +#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */ +#define B43_PHYROUTE_BASE 0x0000 /* Base registers */ +#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */ +#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */ +#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */ + +/* CCK (B-PHY) registers. */ +#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE) /* N-PHY registers. */ -#define B43_PHY_N(reg) (reg) -/* OFDM (A) registers of a G-PHY */ +#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE) +/* N-PHY BMODE registers. */ +#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE) +/* OFDM (A-PHY) registers. */ #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY) -/* Extended G-PHY registers */ +/* Extended G-PHY registers. */ #define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY) /* OFDM (A) PHY Registers */ @@ -79,20 +83,20 @@ struct b43_phy; #define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */ /* CCK (B) PHY Registers */ -#define B43_PHY_VERSION_CCK B43_PHY_BASE(0x00) /* Versioning register for B-PHY */ -#define B43_PHY_CCKBBANDCFG B43_PHY_BASE(0x01) /* Contains antenna 0/1 control bit */ -#define B43_PHY_PGACTL B43_PHY_BASE(0x15) /* PGA control */ +#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */ +#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */ +#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */ #define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */ #define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */ #define B43_PHY_PGACTL_UNKNOWN 0xEFA0 -#define B43_PHY_FBCTL1 B43_PHY_BASE(0x18) /* Frequency bandwidth control 1 */ -#define B43_PHY_ITSSI B43_PHY_BASE(0x29) /* Idle TSSI */ -#define B43_PHY_LO_LEAKAGE B43_PHY_BASE(0x2D) /* Measured LO leakage */ -#define B43_PHY_ENERGY B43_PHY_BASE(0x33) /* Energy */ -#define B43_PHY_SYNCCTL B43_PHY_BASE(0x35) -#define B43_PHY_FBCTL2 B43_PHY_BASE(0x38) /* Frequency bandwidth control 2 */ -#define B43_PHY_DACCTL B43_PHY_BASE(0x60) /* DAC control */ -#define B43_PHY_RCCALOVER B43_PHY_BASE(0x78) /* RC calibration override */ +#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */ +#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */ +#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */ +#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */ +#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35) +#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */ +#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */ +#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */ /* Extended G-PHY Registers */ #define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */ |