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author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-06 21:26:05 (GMT) |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-06 21:26:05 (GMT) |
commit | ffa009c366e33f3eae48bba2547051fe15795f64 (patch) | |
tree | 78736a4ee7c16819830a32a313867e3a88ac6aff /drivers/pci/dmar.c | |
parent | 8e320d02718d2872d52ef88a69a493e420494269 (diff) | |
parent | 46f06b72378d3187f0d12f7a60d020676bfbf332 (diff) | |
download | linux-fsl-qoriq-ffa009c366e33f3eae48bba2547051fe15795f64.tar.xz |
Merge git://git.infradead.org/iommu-2.6
* git://git.infradead.org/iommu-2.6:
drivers/pci/intr_remapping.c: include acpi.h
intel-iommu: Fix oops in device_to_iommu() when devices not found.
intel-iommu: Handle PCI domains appropriately.
intel-iommu: Fix device-to-iommu mapping for PCI-PCI bridges.
x2apic/intr-remap: decouple interrupt remapping from x2apic
x86, dmar: check if it's initialized before disable queue invalidation
intel-iommu: set compatibility format interrupt
Intel IOMMU Suspend/Resume Support - Interrupt Remapping
Intel IOMMU Suspend/Resume Support - Queued Invalidation
Intel IOMMU Suspend/Resume Support - DMAR
intel-iommu: Add for_each_iommu() and for_each_active_iommu() macros
Diffstat (limited to 'drivers/pci/dmar.c')
-rw-r--r-- | drivers/pci/dmar.c | 71 |
1 files changed, 56 insertions, 15 deletions
diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c index d313039..25a00ce 100644 --- a/drivers/pci/dmar.c +++ b/drivers/pci/dmar.c @@ -180,6 +180,7 @@ dmar_parse_one_drhd(struct acpi_dmar_header *header) dmaru->hdr = header; drhd = (struct acpi_dmar_hardware_unit *)header; dmaru->reg_base_addr = drhd->address; + dmaru->segment = drhd->segment; dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ ret = alloc_iommu(dmaru); @@ -790,14 +791,41 @@ end: } /* + * Enable queued invalidation. + */ +static void __dmar_enable_qi(struct intel_iommu *iommu) +{ + u32 cmd, sts; + unsigned long flags; + struct q_inval *qi = iommu->qi; + + qi->free_head = qi->free_tail = 0; + qi->free_cnt = QI_LENGTH; + + spin_lock_irqsave(&iommu->register_lock, flags); + + /* write zero to the tail reg */ + writel(0, iommu->reg + DMAR_IQT_REG); + + dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc)); + + cmd = iommu->gcmd | DMA_GCMD_QIE; + iommu->gcmd |= DMA_GCMD_QIE; + writel(cmd, iommu->reg + DMAR_GCMD_REG); + + /* Make sure hardware complete it */ + IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); + + spin_unlock_irqrestore(&iommu->register_lock, flags); +} + +/* * Enable Queued Invalidation interface. This is a must to support * interrupt-remapping. Also used by DMA-remapping, which replaces * register based IOTLB invalidation. */ int dmar_enable_qi(struct intel_iommu *iommu) { - u32 cmd, sts; - unsigned long flags; struct q_inval *qi; if (!ecap_qis(iommu->ecap)) @@ -835,19 +863,7 @@ int dmar_enable_qi(struct intel_iommu *iommu) spin_lock_init(&qi->q_lock); - spin_lock_irqsave(&iommu->register_lock, flags); - /* write zero to the tail reg */ - writel(0, iommu->reg + DMAR_IQT_REG); - - dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc)); - - cmd = iommu->gcmd | DMA_GCMD_QIE; - iommu->gcmd |= DMA_GCMD_QIE; - writel(cmd, iommu->reg + DMAR_GCMD_REG); - - /* Make sure hardware complete it */ - IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); - spin_unlock_irqrestore(&iommu->register_lock, flags); + __dmar_enable_qi(iommu); return 0; } @@ -1102,3 +1118,28 @@ int __init enable_drhd_fault_handling(void) return 0; } + +/* + * Re-enable Queued Invalidation interface. + */ +int dmar_reenable_qi(struct intel_iommu *iommu) +{ + if (!ecap_qis(iommu->ecap)) + return -ENOENT; + + if (!iommu->qi) + return -ENOENT; + + /* + * First disable queued invalidation. + */ + dmar_disable_qi(iommu); + /* + * Then enable queued invalidation again. Since there is no pending + * invalidation requests now, it's safe to re-enable queued + * invalidation. + */ + __dmar_enable_qi(iommu); + + return 0; +} |