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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-14 05:02:00 (GMT) |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-14 05:02:00 (GMT) |
commit | 2f466d33f5f60542d3d82c0477de5863b22c94b9 (patch) | |
tree | 839972958941d55852a9af270b04af09e3147116 /drivers/pci/host/pci-exynos.c | |
parent | f9300eaaac1ca300083ad41937923a90cc3a2394 (diff) | |
parent | eaaeb1cb33310dea6c3fa45d8bfc63e5a1d0a846 (diff) | |
download | linux-fsl-qoriq-2f466d33f5f60542d3d82c0477de5863b22c94b9.tar.xz |
Merge tag 'pci-v3.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas:
"Resource management
- Fix host bridge window coalescing (Alexey Neyman)
- Pass type, width, and prefetchability for window alignment (Wei Yang)
PCI device hotplug
- Convert acpiphp, acpiphp_ibm to dynamic debug (Lan Tianyu)
Power management
- Remove pci_pm_complete() (Liu Chuansheng)
MSI
- Fail initialization if device is not in PCI_D0 (Yijing Wang)
MPS (Max Payload Size)
- Use pcie_get_mps() and pcie_set_mps() to simplify code (Yijing Wang)
- Use pcie_set_readrq() to simplify code (Yijing Wang)
- Use cached pci_dev->pcie_mpss to simplify code (Yijing Wang)
SR-IOV
- Enable upstream bridges even for VFs on virtual buses (Bjorn Helgaas)
- Use pci_is_root_bus() to avoid catching virtual buses (Wei Yang)
Virtualization
- Add x86 MSI masking ops (Konrad Rzeszutek Wilk)
Freescale i.MX6
- Support i.MX6 PCIe controller (Sean Cross)
- Increase link startup timeout (Marek Vasut)
- Probe PCIe in fs_initcall() (Marek Vasut)
- Fix imprecise abort handler (Tim Harvey)
- Remove redundant of_match_ptr (Sachin Kamat)
Renesas R-Car
- Support Gen2 internal PCIe controller (Valentine Barshak)
Samsung Exynos
- Add MSI support (Jingoo Han)
- Turn off power when link fails (Jingoo Han)
- Add Jingoo Han as maintainer (Jingoo Han)
- Add clk_disable_unprepare() on error path (Wei Yongjun)
- Remove redundant of_match_ptr (Sachin Kamat)
Synopsys DesignWare
- Add irq_create_mapping() (Pratyush Anand)
- Add header guards (Seungwon Jeon)
Miscellaneous
- Enable native PCIe services by default on non-ACPI (Andrew Murray)
- Cleanup _OSC usage and messages (Bjorn Helgaas)
- Remove pcibios_last_bus boot option on non-x86 (Bjorn Helgaas)
- Convert bus code to use bus_, drv_, and dev_groups (Greg Kroah-Hartman)
- Remove unused pci_mem_start (Myron Stowe)
- Make sysfs functions static (Sachin Kamat)
- Warn on invalid return from driver probe (Stephen M. Cameron)
- Remove Intel Haswell D3 delays (Todd E Brandt)
- Call pci_set_master() in core if driver doesn't do it (Yinghai Lu)
- Use pci_is_pcie() to simplify code (Yijing Wang)
- Use PCIe capability accessors to simplify code (Yijing Wang)
- Use cached pci_dev->pcie_cap to simplify code (Yijing Wang)
- Removed unused "is_pcie" from struct pci_dev (Yijing Wang)
- Simplify sysfs CPU affinity implementation (Yijing Wang)"
* tag 'pci-v3.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (79 commits)
PCI: Enable upstream bridges even for VFs on virtual buses
PCI: Add pci_upstream_bridge()
PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq()
PCI: Warn on driver probe return value greater than zero
PCI: Drop warning about drivers that don't use pci_set_master()
PCI: Workaround missing pci_set_master in pci drivers
powerpc/pci: Use pci_is_pcie() to simplify code [fix]
PCI: Update pcie_ports 'auto' behavior for non-ACPI platforms
PCI: imx6: Probe the PCIe in fs_initcall()
PCI: Add R-Car Gen2 internal PCI support
PCI: imx6: Remove redundant of_match_ptr
PCI: Report pci_pme_active() kmalloc failure
mn10300/PCI: Remove useless pcibios_last_bus
frv/PCI: Remove pcibios_last_bus
PCI: imx6: Increase link startup timeout
PCI: exynos: Remove redundant of_match_ptr
PCI: imx6: Fix imprecise abort handler
PCI: Fail MSI/MSI-X initialization if device is not in PCI_D0
PCI: imx6: Remove redundant dev_err() in imx6_pcie_probe()
x86/PCI: Coalesce multiple overlapping host bridge windows
...
Diffstat (limited to 'drivers/pci/host/pci-exynos.c')
-rw-r--r-- | drivers/pci/host/pci-exynos.c | 132 |
1 files changed, 125 insertions, 7 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 94e096b..24beed3 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -48,6 +48,7 @@ struct exynos_pcie { #define PCIE_IRQ_SPECIAL 0x008 #define PCIE_IRQ_EN_PULSE 0x00c #define PCIE_IRQ_EN_LEVEL 0x010 +#define IRQ_MSI_ENABLE (0x1 << 2) #define PCIE_IRQ_EN_SPECIAL 0x014 #define PCIE_PWR_RESET 0x018 #define PCIE_CORE_RESET 0x01c @@ -77,18 +78,28 @@ struct exynos_pcie { #define PCIE_PHY_PLL_BIAS 0x00c #define PCIE_PHY_DCC_FEEDBACK 0x014 #define PCIE_PHY_PLL_DIV_1 0x05c +#define PCIE_PHY_COMMON_POWER 0x064 +#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3) #define PCIE_PHY_TRSV0_EMP_LVL 0x084 #define PCIE_PHY_TRSV0_DRV_LVL 0x088 #define PCIE_PHY_TRSV0_RXCDR 0x0ac +#define PCIE_PHY_TRSV0_POWER 0x0c4 +#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV0_LVCC 0x0dc #define PCIE_PHY_TRSV1_EMP_LVL 0x144 #define PCIE_PHY_TRSV1_RXCDR 0x16c +#define PCIE_PHY_TRSV1_POWER 0x184 +#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV1_LVCC 0x19c #define PCIE_PHY_TRSV2_EMP_LVL 0x204 #define PCIE_PHY_TRSV2_RXCDR 0x22c +#define PCIE_PHY_TRSV2_POWER 0x244 +#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV2_LVCC 0x25c #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 #define PCIE_PHY_TRSV3_RXCDR 0x2ec +#define PCIE_PHY_TRSV3_POWER 0x304 +#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) #define PCIE_PHY_TRSV3_LVCC 0x31c static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) @@ -202,6 +213,58 @@ static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET); } +static void exynos_pcie_power_on_phy(struct pcie_port *pp) +{ + u32 val; + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); + val &= ~PCIE_PHY_COMMON_PD_CMN; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); + val &= ~PCIE_PHY_TRSV0_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); + val &= ~PCIE_PHY_TRSV1_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); + val &= ~PCIE_PHY_TRSV2_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); + val &= ~PCIE_PHY_TRSV3_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); +} + +static void exynos_pcie_power_off_phy(struct pcie_port *pp) +{ + u32 val; + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); + val |= PCIE_PHY_COMMON_PD_CMN; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); + val |= PCIE_PHY_TRSV0_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); + val |= PCIE_PHY_TRSV1_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); + val |= PCIE_PHY_TRSV2_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); + + val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); + val |= PCIE_PHY_TRSV3_PD_TSV; + exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); +} + static void exynos_pcie_init_phy(struct pcie_port *pp) { struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); @@ -270,6 +333,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) /* de-assert phy reset */ exynos_pcie_deassert_phy_reset(pp); + /* power on phy */ + exynos_pcie_power_on_phy(pp); + /* initialize phy */ exynos_pcie_init_phy(pp); @@ -302,6 +368,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) PCIE_PHY_PLL_LOCKED); dev_info(pp->dev, "PLL Locked: 0x%x\n", val); } + /* power off phy */ + exynos_pcie_power_off_phy(pp); + dev_err(pp->dev, "PCIe Link Fail\n"); return -EINVAL; } @@ -342,9 +411,36 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) return IRQ_HANDLED; } +static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg) +{ + struct pcie_port *pp = arg; + + dw_handle_msi_irq(pp); + + return IRQ_HANDLED; +} + +static void exynos_pcie_msi_init(struct pcie_port *pp) +{ + u32 val; + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); + + dw_pcie_msi_init(pp); + + /* enable MSI interrupt */ + val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL); + val |= IRQ_MSI_ENABLE; + exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL); + return; +} + static void exynos_pcie_enable_interrupts(struct pcie_port *pp) { exynos_pcie_enable_irq_pulse(pp); + + if (IS_ENABLED(CONFIG_PCI_MSI)) + exynos_pcie_msi_init(pp); + return; } @@ -430,6 +526,22 @@ static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev) return ret; } + if (IS_ENABLED(CONFIG_PCI_MSI)) { + pp->msi_irq = platform_get_irq(pdev, 0); + if (!pp->msi_irq) { + dev_err(&pdev->dev, "failed to get msi irq\n"); + return -ENODEV; + } + + ret = devm_request_irq(&pdev->dev, pp->msi_irq, + exynos_pcie_msi_irq_handler, + IRQF_SHARED, "exynos-pcie", pp); + if (ret) { + dev_err(&pdev->dev, "failed to request msi irq\n"); + return ret; + } + } + pp->root_bus_nr = -1; pp->ops = &exynos_pcie_host_ops; @@ -487,18 +599,24 @@ static int __init exynos_pcie_probe(struct platform_device *pdev) elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base); - if (IS_ERR(exynos_pcie->elbi_base)) - return PTR_ERR(exynos_pcie->elbi_base); + if (IS_ERR(exynos_pcie->elbi_base)) { + ret = PTR_ERR(exynos_pcie->elbi_base); + goto fail_bus_clk; + } phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1); exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base); - if (IS_ERR(exynos_pcie->phy_base)) - return PTR_ERR(exynos_pcie->phy_base); + if (IS_ERR(exynos_pcie->phy_base)) { + ret = PTR_ERR(exynos_pcie->phy_base); + goto fail_bus_clk; + } block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2); exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base); - if (IS_ERR(exynos_pcie->block_base)) - return PTR_ERR(exynos_pcie->block_base); + if (IS_ERR(exynos_pcie->block_base)) { + ret = PTR_ERR(exynos_pcie->block_base); + goto fail_bus_clk; + } ret = add_pcie_port(pp, pdev); if (ret < 0) @@ -535,7 +653,7 @@ static struct platform_driver exynos_pcie_driver = { .driver = { .name = "exynos-pcie", .owner = THIS_MODULE, - .of_match_table = of_match_ptr(exynos_pcie_of_match), + .of_match_table = exynos_pcie_of_match, }, }; |