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| author | Mohit Kumar <mohit.kumar@st.com> | 2014-02-19 12:04:35 (GMT) |
|---|---|---|
| committer | Jiri Slaby <jslaby@suse.cz> | 2014-05-05 12:24:35 (GMT) |
| commit | 47495e3596d95047168e4a831b2a8ccdf7efafaa (patch) | |
| tree | e0b37c395c2b3be6ce3523a29321a8db5d4c34d5 /drivers/pci/rom.c | |
| parent | 6226a60b08a72290df15598d4355a42bcf4bb65d (diff) | |
| download | linux-fsl-qoriq-47495e3596d95047168e4a831b2a8ccdf7efafaa.tar.xz | |
PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory BAR
commit dbffdd6862e67d60703f2df66c558bf448f81d6e upstream.
The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1).
The BARs can be configured as follows:
- One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR
- Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
This patch corrects 64-bit, non-prefetchable memory BAR configuration
implemented in dw driver.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Diffstat (limited to 'drivers/pci/rom.c')
0 files changed, 0 insertions, 0 deletions