diff options
| author | Lucas Stach <l.stach@pengutronix.de> | 2014-07-23 17:52:38 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:37:01 (GMT) |
| commit | 1805601447a2f00dcf2cef7ebc6b6fe940b613a6 (patch) | |
| tree | ea79d8eedbf76f9d78e4cfd360255ecc3d521305 /drivers/pci | |
| parent | a767dda446279d3c55c9871647449c90ba8e445b (diff) | |
| download | linux-fsl-qoriq-1805601447a2f00dcf2cef7ebc6b6fe940b613a6.tar.xz | |
PCI: designware: Parse bus-range property from devicetree
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.
Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.
[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6
Change-Id: Ib2a849e0d1399b16eaafccfdb2c77e6d4fc916bc
Reviewed-on: http://git.am.freescale.net:8181/19700
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 11 | ||||
| -rw-r--r-- | drivers/pci/host/pcie-designware.h | 1 |
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 76d3d8e..561fa30 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -500,6 +500,16 @@ int __init dw_pcie_host_init(struct pcie_port *pp) } } + ret = of_pci_parse_bus_range(np, &pp->busn); + if (ret < 0) { + pp->busn.name = np->name; + pp->busn.start = 0; + pp->busn.end = 0xff; + pp->busn.flags = IORESOURCE_BUS; + dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n", + ret, &pp->busn); + } + if (!pp->dbi_base) { pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, resource_size(&pp->cfg)); @@ -794,6 +804,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr; pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); + pci_add_resource(&sys->resources, &pp->busn); return 1; } diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 3e84e0a..a476e60 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -48,6 +48,7 @@ struct pcie_port { struct resource cfg; struct resource io; struct resource mem; + struct resource busn; struct pcie_port_info config; int irq; u32 lanes; |