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| author | Mohit Kumar <mohit.kumar@st.com> | 2014-04-14 20:22:54 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:36:55 (GMT) |
| commit | 9a39a423c659246b7b772c5244b72adb88166704 (patch) | |
| tree | 57ebd235486a230a2eb622837fcd769c192f5fd4 /drivers/pci | |
| parent | 5fd84fda07810d8aa8408ed642064834d8b86930 (diff) | |
| download | linux-fsl-qoriq-9a39a423c659246b7b772c5244b72adb88166704.tar.xz | |
PCI: designware: Fix comment for setting number of lanes
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=66c5c34bf80c28d370eb9bcf30153ea0304a288a
Change-Id: I7e20ddc2d977de0fb9eb29d3f4ba6163077aabcf
Reviewed-on: http://git.am.freescale.net:8181/19691
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pcie-designware.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 6eca144..a9a62ce 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -764,7 +764,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) u32 membase; u32 memlimit; - /* set the number of lines as 4 */ + /* set the number of lanes */ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); val &= ~PORT_LINK_MODE_MASK; switch (pp->lanes) { |