diff options
| author | Chew, Chiau Ee <chiau.ee.chew@intel.com> | 2013-11-28 18:13:11 (GMT) |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2013-11-28 11:23:37 (GMT) |
| commit | c50325f7bcb8a3ceaacb9dbc41180b1cbbae7b5e (patch) | |
| tree | a1a133a87129f779abad37eaa3861b84f7ddc816 /drivers/spi | |
| parent | 54acbd9688e6324470671525c7916011f1ff8081 (diff) | |
| download | linux-fsl-qoriq-c50325f7bcb8a3ceaacb9dbc41180b1cbbae7b5e.tar.xz | |
spi/pxa2xx: Restore private register bits.
The Intel LPSS SPI private register bits have to be restored
when system resume from S3 suspend.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 7028180..7765b19 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1293,6 +1293,9 @@ static int pxa2xx_spi_resume(struct device *dev) /* Enable the SSP clock */ clk_prepare_enable(ssp->clk); + /* Restore LPSS private register bits */ + lpss_ssp_setup(drv_data); + /* Start the queue running */ status = spi_master_resume(drv_data->master); if (status != 0) { |