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author | Andres Salomon <dilinger@queued.net> | 2010-09-25 02:13:42 (GMT) |
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committer | Greg Kroah-Hartman <gregkh@suse.de> | 2010-09-30 01:01:40 (GMT) |
commit | eecb3e4e5d9d83ebe1bef222a707eb7618498b67 (patch) | |
tree | 64e1c95f9e7530195f3b7a80fe120932c0fe30b4 /drivers/staging/olpc_dcon/olpc_dcon.h | |
parent | 25417922694e60f04cd4dc8448ada9236f18c532 (diff) | |
download | linux-fsl-qoriq-eecb3e4e5d9d83ebe1bef222a707eb7618498b67.tar.xz |
staging: olpc_dcon: add OLPC display controller (DCON) support
This adds DCON support for the OLPC XO. The DCON is found in XO-1 and
XO-1.5 hardware. The XO-1 has a CS5536 southbridge, while the XO-1.5
has a Via chipset; the GPIO magic that's necessary to communicate with
the DCON chip is unfortunately different across both platforms. This
driver supports both.
This driver is in bad state atm, so I'm requesting its inclusion into
staging so it can be cleaned up while staying in the kernel tree.
Original driver by Dave Woodhouse, and modified extensively by
Jordan Crouse, myself, Deepak Saxena, Paul Fox, Daniel Drake, and
probably others that I've missed.
Signed-off-by: Andres Salomon <dilinger@queued.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/olpc_dcon/olpc_dcon.h')
-rw-r--r-- | drivers/staging/olpc_dcon/olpc_dcon.h | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/drivers/staging/olpc_dcon/olpc_dcon.h b/drivers/staging/olpc_dcon/olpc_dcon.h new file mode 100644 index 0000000..6453ca4 --- /dev/null +++ b/drivers/staging/olpc_dcon/olpc_dcon.h @@ -0,0 +1,75 @@ +#ifndef OLPC_DCON_H_ +#define OLPC_DCON_H_ + +/* DCON registers */ + +#define DCON_REG_ID 0 +#define DCON_REG_MODE 1 + +#define MODE_PASSTHRU (1<<0) +#define MODE_SLEEP (1<<1) +#define MODE_SLEEP_AUTO (1<<2) +#define MODE_BL_ENABLE (1<<3) +#define MODE_BLANK (1<<4) +#define MODE_CSWIZZLE (1<<5) +#define MODE_COL_AA (1<<6) +#define MODE_MONO_LUMA (1<<7) +#define MODE_SCAN_INT (1<<8) +#define MODE_CLOCKDIV (1<<9) +#define MODE_DEBUG (1<<14) +#define MODE_SELFTEST (1<<15) + +#define DCON_REG_HRES 2 +#define DCON_REG_HTOTAL 3 +#define DCON_REG_HSYNC_WIDTH 4 +#define DCON_REG_VRES 5 +#define DCON_REG_VTOTAL 6 +#define DCON_REG_VSYNC_WIDTH 7 +#define DCON_REG_TIMEOUT 8 +#define DCON_REG_SCAN_INT 9 +#define DCON_REG_BRIGHT 10 + +/* GPIO registers (CS5536) */ + +#define MSR_LBAR_GPIO 0x5140000C + +#define GPIOx_OUT_VAL 0x00 +#define GPIOx_OUT_EN 0x04 +#define GPIOx_IN_EN 0x20 +#define GPIOx_INV_EN 0x24 +#define GPIOx_IN_FLTR_EN 0x28 +#define GPIOx_EVNTCNT_EN 0x2C +#define GPIOx_READ_BACK 0x30 +#define GPIOx_EVNT_EN 0x38 +#define GPIOx_NEGEDGE_EN 0x44 +#define GPIOx_NEGEDGE_STS 0x4C +#define GPIO_FLT7_AMNT 0xD8 +#define GPIO_MAP_X 0xE0 +#define GPIO_MAP_Y 0xE4 +#define GPIO_FE7_SEL 0xF7 + + +/* Status values */ + +#define DCONSTAT_SCANINT 0 +#define DCONSTAT_SCANINT_DCON 1 +#define DCONSTAT_DISPLAYLOAD 2 +#define DCONSTAT_MISSED 3 + +/* Source values */ + +#define DCON_SOURCE_DCON 0 +#define DCON_SOURCE_CPU 1 + +/* Output values */ +#define DCON_OUTPUT_COLOR 0 +#define DCON_OUTPUT_MONO 1 + +/* Sleep values */ +#define DCON_ACTIVE 0 +#define DCON_SLEEP 1 + +/* Interrupt */ +#define DCON_IRQ 6 + +#endif |