Rewind v3.13-rc3+ (78fd82238d0e5716) to v3.12

8 files changed, 428 insertions, 97 deletions

diff --git a/drivers/staging/winbond/core.h b/drivers/staging/winbond/core.h
index fc0ef24..6160b2f 100644
--- a/drivers/staging/winbond/core.h
+++ b/drivers/staging/winbond/core.h
@@ -18,8 +18,8 @@
 struct mlme_frame {
 	s8		*pMMPDU;
 	u16		len;
-	u8		data_type;
-	u8		is_in_used;
+	u8		DataType;
+	u8		IsInUsed;
 
 	u8		TxMMPDU[MAX_NUM_TX_MMPDU][MAX_MMPDU_SIZE];
 	u8		TxMMPDUInUse[(MAX_NUM_TX_MMPDU + 3) & ~0x03];
@@ -52,9 +52,13 @@ struct wbsoft_priv {
 	struct hw_data sHwData;	/*For HAL */
 	struct wb35_mds Mds;
 
+	atomic_t ThreadCount;
+
 	u32 RxByteCount;
 	u32 TxByteCount;
 
+	u8 LinkName[WB_MAX_LINK_NAME_LEN];
+
 	bool enabled;
 };
 
diff --git a/drivers/staging/winbond/mds.c b/drivers/staging/winbond/mds.c
index cac7720..fcc3d21 100644
--- a/drivers/staging/winbond/mds.c
+++ b/drivers/staging/winbond/mds.c
@@ -412,7 +412,7 @@ static void MLME_GetNextPacket(struct wbsoft_priv *adapter,
 	desc->buffer_size[desc->InternalUsed] = adapter->sMlmeFrame.len;
 	desc->buffer_total_size += adapter->sMlmeFrame.len;
 	desc->buffer_number++;
-	desc->Type = adapter->sMlmeFrame.data_type;
+	desc->Type = adapter->sMlmeFrame.DataType;
 }
 
 static void MLMEfreeMMPDUBuffer(struct wbsoft_priv *adapter, s8 *pData)
@@ -440,7 +440,7 @@ static void MLME_SendComplete(struct wbsoft_priv *adapter, u8 PacketID,
 	MLMEfreeMMPDUBuffer(adapter, adapter->sMlmeFrame.pMMPDU);
 
 	/* Return resource */
-	adapter->sMlmeFrame.is_in_used = PACKET_FREE_TO_USE;
+	adapter->sMlmeFrame.IsInUsed = PACKET_FREE_TO_USE;
 }
 
 void
diff --git a/drivers/staging/winbond/mto.c b/drivers/staging/winbond/mto.c
index b031ecd..560c0ab 100644
--- a/drivers/staging/winbond/mto.c
+++ b/drivers/staging/winbond/mto.c
@@ -21,7 +21,6 @@
 #include "wbhal.h"
 #include "wb35reg_f.h"
 #include "core.h"
-#include "mto.h"
 
 /* Declare SQ3 to rate and fragmentation threshold table */
 /* Declare fragmentation threshold table */
@@ -46,6 +45,12 @@ static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS];
 
 static u8 boSparseTxTraffic;
 
+void MTO_Init(struct wbsoft_priv *adapter);
+void TxRateReductionCtrl(struct wbsoft_priv *adapter);
+void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index);
+void MTO_TxFailed(struct wbsoft_priv *adapter);
+void hal_get_dto_para(struct wbsoft_priv *adapter, char *buffer);
+
 /*
  * ===========================================================================
  * MTO_Init --
diff --git a/drivers/staging/winbond/mto.h b/drivers/staging/winbond/mto.h
index 8d41eed..a0f659c 100644
--- a/drivers/staging/winbond/mto.h
+++ b/drivers/staging/winbond/mto.h
@@ -127,8 +127,12 @@ extern u16 MTO_Frag_Th_Tbl[];
 #define MTO_DATA_RATE()			MTO_Data_Rate_Tbl[MTO_RATE_LEVEL()]
 #define MTO_FRAG_TH()			MTO_Frag_Th_Tbl[MTO_FRAG_TH_LEVEL()]
 
-void MTO_Init(struct wbsoft_priv *);
-void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index);
+extern void MTO_Init(struct wbsoft_priv *);
+extern void MTO_PeriodicTimerExpired(struct wbsoft_priv *);
+extern void MTO_SetDTORateRange(struct wbsoft_priv *, u8 *, u8);
+extern u8 MTO_GetTxRate(struct wbsoft_priv *adapter, u32 fpdu_len);
+extern u8 MTO_GetTxFallbackRate(struct wbsoft_priv *adapter);
+extern void MTO_SetTxCount(struct wbsoft_priv *adapter, u8 t0, u8 index);
 
 #endif /* __MTO_H__ */
 
diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c
index 8aecced..cfbfbbb 100644
--- a/drivers/staging/winbond/phy_calibration.c
+++ b/drivers/staging/winbond/phy_calibration.c
@@ -27,12 +27,10 @@
 #define DEG2RAD(X)      (0.017453 * (X))
 
 static const s32 Angles[] = {
-	FIXED(DEG2RAD(45.0)),     FIXED(DEG2RAD(26.565)),
-	FIXED(DEG2RAD(14.0362)),  FIXED(DEG2RAD(7.12502)),
-	FIXED(DEG2RAD(3.57633)),  FIXED(DEG2RAD(1.78991)),
-	FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)),
-	FIXED(DEG2RAD(0.223811)), FIXED(DEG2RAD(0.111906)),
-	FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977))
+	FIXED(DEG2RAD(45.0)),     FIXED(DEG2RAD(26.565)),   FIXED(DEG2RAD(14.0362)),
+	FIXED(DEG2RAD(7.12502)),  FIXED(DEG2RAD(3.57633)),  FIXED(DEG2RAD(1.78991)),
+	FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)), FIXED(DEG2RAD(0.223811)),
+	FIXED(DEG2RAD(0.111906)), FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977))
 };
 
 /****************** LOCAL FUNCTION DECLARATION SECTION **********************/
@@ -44,7 +42,7 @@ static const s32 Angles[] = {
 
 /****************** FUNCTION DEFINITION SECTION *****************************/
 
-static s32 _s13_to_s32(u32 data)
+s32 _s13_to_s32(u32 data)
 {
 	u32     val;
 
@@ -56,8 +54,22 @@ static s32 _s13_to_s32(u32 data)
 	return (s32) val;
 }
 
+u32 _s32_to_s13(s32 data)
+{
+	u32     val;
+
+	if (data > 4095)
+		data = 4095;
+	else if (data < -4096)
+		data = -4096;
+
+	val = data & 0x1FFF;
+
+	return val;
+}
+
 /****************************************************************************/
-static s32 _s4_to_s32(u32 data)
+s32 _s4_to_s32(u32 data)
 {
 	s32     val;
 
@@ -69,7 +81,7 @@ static s32 _s4_to_s32(u32 data)
 	return val;
 }
 
-static u32 _s32_to_s4(s32 data)
+u32 _s32_to_s4(s32 data)
 {
 	u32     val;
 
@@ -84,7 +96,7 @@ static u32 _s32_to_s4(s32 data)
 }
 
 /****************************************************************************/
-static s32 _s5_to_s32(u32 data)
+s32 _s5_to_s32(u32 data)
 {
 	s32     val;
 
@@ -96,7 +108,7 @@ static s32 _s5_to_s32(u32 data)
 	return val;
 }
 
-static u32 _s32_to_s5(s32 data)
+u32 _s32_to_s5(s32 data)
 {
 	u32     val;
 
@@ -111,7 +123,7 @@ static u32 _s32_to_s5(s32 data)
 }
 
 /****************************************************************************/
-static s32 _s6_to_s32(u32 data)
+s32 _s6_to_s32(u32 data)
 {
 	s32     val;
 
@@ -123,7 +135,7 @@ static s32 _s6_to_s32(u32 data)
 	return val;
 }
 
-static u32 _s32_to_s6(s32 data)
+u32 _s32_to_s6(s32 data)
 {
 	u32     val;
 
@@ -138,7 +150,34 @@ static u32 _s32_to_s6(s32 data)
 }
 
 /****************************************************************************/
-static s32 _floor(s32 n)
+s32 _s9_to_s32(u32 data)
+{
+	s32     val;
+
+	val = data & 0x00FF;
+
+	if ((data & BIT(8)) != 0)
+		val |= 0xFFFFFF00;
+
+	return val;
+}
+
+u32 _s32_to_s9(s32 data)
+{
+	u32     val;
+
+	if (data > 255)
+		data = 255;
+	else if (data < -256)
+		data = -256;
+
+	val = data & 0x01FF;
+
+	return val;
+}
+
+/****************************************************************************/
+s32 _floor(s32 n)
 {
 	if (n > 0)
 		n += 5;
@@ -154,7 +193,7 @@ static s32 _floor(s32 n)
  * sqsum is the input and the output is sq_rt;
  * The maximum of sqsum = 2^27 -1;
  */
-static u32 _sqrt(u32 sqsum)
+u32 _sqrt(u32 sqsum)
 {
 	u32     sq_rt;
 
@@ -222,7 +261,7 @@ static u32 _sqrt(u32 sqsum)
 }
 
 /****************************************************************************/
-static void _sin_cos(s32 angle, s32 *sin, s32 *cos)
+void _sin_cos(s32 angle, s32 *sin, s32 *cos)
 {
 	s32 X, Y, TargetAngle, CurrAngle;
 	unsigned    Step;
@@ -257,8 +296,7 @@ static void _sin_cos(s32 angle, s32 *sin, s32 *cos)
 	}
 }
 
-static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number,
-				     u32 *pValue)
+static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number, u32 *pValue)
 {
 	if (number < 0x1000)
 		number += 0x1000;
@@ -266,8 +304,7 @@ static unsigned char hal_get_dxx_reg(struct hw_data *pHwData, u16 number,
 }
 #define hw_get_dxx_reg(_A, _B, _C) hal_get_dxx_reg(_A, _B, (u32 *)_C)
 
-static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number,
-				     u32 value)
+static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number, u32 value)
 {
 	unsigned char ret;
 
@@ -279,7 +316,7 @@ static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number,
 #define hw_set_dxx_reg(_A, _B, _C) hal_set_dxx_reg(_A, _B, (u32)_C)
 
 
-static void _reset_rx_cal(struct hw_data *phw_data)
+void _reset_rx_cal(struct hw_data *phw_data)
 {
 	u32     val;
 
@@ -299,7 +336,7 @@ static void _reset_rx_cal(struct hw_data *phw_data)
 
 
 /**********************************************/
-static void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
+void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
 {
 	u32     reg_agc_ctrl3;
 	u32     reg_a_acq_ctrl;
@@ -370,8 +407,7 @@ static void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32
 	PHY_DEBUG(("[CAL]    ** adc_dc_cal_i = %d (0x%04X)\n",
 			   _s9_to_s32(val&0x000001FF), val&0x000001FF));
 	PHY_DEBUG(("[CAL]    ** adc_dc_cal_q = %d (0x%04X)\n",
-			   _s9_to_s32((val&0x0003FE00)>>9),
-			   (val&0x0003FE00)>>9));
+			   _s9_to_s32((val&0x0003FE00)>>9), (val&0x0003FE00)>>9));
 #endif
 
 	hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val);
@@ -394,8 +430,249 @@ static void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32
 	hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
 }
 
+/****************************************************************/
+void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
+{
+	u32     reg_agc_ctrl3;
+	u32     reg_mode_ctrl;
+	u32     reg_dc_cancel;
+	s32     iqcal_image_i;
+	s32     iqcal_image_q;
+	u32     sqsum;
+	s32     mag_0;
+	s32     mag_1;
+	s32     fix_cancel_dc_i = 0;
+	u32     val;
+	int     loop;
+
+	PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
+
+	/* a. Set to "TX calibration mode" */
+
+	/* 0x01 0xEE3FC2  ; 3B8FF  ; Calibration (6a). enable TX IQ calibration loop circuits */
+	phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
+	/* 0x0B 0x1905D6  ; 06417  ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
+	phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
+	/* 0x05 0x24C60A  ; 09318  ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
+	phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
+	/* 0x06 0x06880C  ; 01A20  ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
+	phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
+	/* 0x00 0xFDF1C0  ; 3F7C7  ; Calibration (6e). turn on IQ imbalance/Test mode */
+	phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
+
+	hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
+
+	/* a. Disable AGC */
+	hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
+	reg_agc_ctrl3 &= ~BIT(2);
+	reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
+	hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
+
+	hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
+	val |= MASK_AGC_FIX_GAIN;
+	hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
+
+	/* b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 */
+	hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
+
+	PHY_DEBUG(("[CAL]    MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
+	reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
+
+	/* mode=2, tone=0 */
+	/* reg_mode_ctrl |= (MASK_CALIB_START|2); */
+
+	/* mode=2, tone=1 */
+	/* reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); */
+
+	/* mode=2, tone=2 */
+	reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2));
+	hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
+	PHY_DEBUG(("[CAL]    MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
+
+	hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
+	PHY_DEBUG(("[CAL]    DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
+
+	for (loop = 0; loop < LOOP_TIMES; loop++) {
+		PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
+
+		/* c. reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */
+		reg_dc_cancel &= ~(0x03FF);
+		PHY_DEBUG(("[CAL]    DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
+		hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
+
+		hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
+		PHY_DEBUG(("[CAL]    CALIB_READ2 = 0x%08X\n", val));
+
+		iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
+		iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
+		sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
+		mag_0 = (s32) _sqrt(sqsum);
+		PHY_DEBUG(("[CAL]    mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
+				   mag_0, iqcal_image_i, iqcal_image_q));
+
+		/* d. */
+		reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT);
+		PHY_DEBUG(("[CAL]    DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
+		hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
+
+		hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
+		PHY_DEBUG(("[CAL]    CALIB_READ2 = 0x%08X\n", val));
+
+		iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
+		iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
+		sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
+		mag_1 = (s32) _sqrt(sqsum);
+		PHY_DEBUG(("[CAL]    mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
+				   mag_1, iqcal_image_i, iqcal_image_q));
+
+		/* e. Calculate the correct DC offset cancellation value for I */
+		if (mag_0 != mag_1)
+			fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
+		else {
+			if (mag_0 == mag_1)
+				PHY_DEBUG(("[CAL]   ***** mag_0 = mag_1 !!\n"));
+			fix_cancel_dc_i = 0;
+		}
+
+		PHY_DEBUG(("[CAL]    ** fix_cancel_dc_i = %d (0x%04X)\n",
+				   fix_cancel_dc_i, _s32_to_s5(fix_cancel_dc_i)));
+
+		if ((abs(mag_1-mag_0)*6) > mag_0)
+			break;
+	}
+
+	if (loop >= 19)
+		fix_cancel_dc_i = 0;
+
+	reg_dc_cancel &= ~(0x03FF);
+	reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT);
+	hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
+	PHY_DEBUG(("[CAL]    DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
+
+	/* g. */
+	reg_mode_ctrl &= ~MASK_CALIB_START;
+	hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
+	PHY_DEBUG(("[CAL]    MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
+}
+
+/*****************************************************/
+void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
+{
+	u32     reg_agc_ctrl3;
+	u32     reg_mode_ctrl;
+	u32     reg_dc_cancel;
+	s32     iqcal_image_i;
+	s32     iqcal_image_q;
+	u32     sqsum;
+	s32     mag_0;
+	s32     mag_1;
+	s32     fix_cancel_dc_q = 0;
+	u32     val;
+	int     loop;
+
+	PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
+	/*0x01 0xEE3FC2  ; 3B8FF  ; Calibration (6a). enable TX IQ calibration loop circuits */
+	phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
+	/* 0x0B 0x1905D6  ; 06417  ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
+	phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
+	/* 0x05 0x24C60A  ; 09318  ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
+	phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
+	/* 0x06 0x06880C  ; 01A20  ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
+	phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
+	/* 0x00 0xFDF1C0  ; 3F7C7  ; Calibration (6e). turn on IQ imbalance/Test mode */
+	phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
+
+	hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
+
+	/* a. Disable AGC */
+	hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, &reg_agc_ctrl3);
+	reg_agc_ctrl3 &= ~BIT(2);
+	reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
+	hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
+
+	hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
+	val |= MASK_AGC_FIX_GAIN;
+	hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
+
+	/* a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 */
+	hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
+	PHY_DEBUG(("[CAL]    MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
+
+	/* reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); */
+	reg_mode_ctrl &= ~(MASK_IQCAL_MODE);
+	reg_mode_ctrl |= (MASK_CALIB_START|3);
+	hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
+	PHY_DEBUG(("[CAL]    MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
+
+	hw_get_dxx_reg(phw_data, 0x5C, &reg_dc_cancel);
+	PHY_DEBUG(("[CAL]    DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
+
+	for (loop = 0; loop < LOOP_TIMES; loop++) {
+		PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
+
+		/* b. reset cancel_dc_q[4:0] in register DC_Cancel */
+		reg_dc_cancel &= ~(0x001F);
+		PHY_DEBUG(("[CAL]    DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
+		hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
+
+		hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
+		PHY_DEBUG(("[CAL]    CALIB_READ2 = 0x%08X\n", val));
+
+		iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
+		iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
+		sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
+		mag_0 = _sqrt(sqsum);
+		PHY_DEBUG(("[CAL]    mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
+				   mag_0, iqcal_image_i, iqcal_image_q));
+
+		/* c. */
+		reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT);
+		PHY_DEBUG(("[CAL]    DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
+		hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
+
+		hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
+		PHY_DEBUG(("[CAL]    CALIB_READ2 = 0x%08X\n", val));
+
+		iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
+		iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
+		sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
+		mag_1 = _sqrt(sqsum);
+		PHY_DEBUG(("[CAL]    mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
+				   mag_1, iqcal_image_i, iqcal_image_q));
+
+		/* d. Calculate the correct DC offset cancellation value for I */
+		if (mag_0 != mag_1)
+			fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
+		else {
+			if (mag_0 == mag_1)
+				PHY_DEBUG(("[CAL]   ***** mag_0 = mag_1 !!\n"));
+			fix_cancel_dc_q = 0;
+		}
+
+		PHY_DEBUG(("[CAL]    ** fix_cancel_dc_q = %d (0x%04X)\n",
+				   fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q)));
+
+		if ((abs(mag_1-mag_0)*6) > mag_0)
+			break;
+	}
+
+	if (loop >= 19)
+		fix_cancel_dc_q = 0;
+
+	reg_dc_cancel &= ~(0x001F);
+	reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT);
+	hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
+	PHY_DEBUG(("[CAL]    DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
+
+
+	/* f. */
+	reg_mode_ctrl &= ~MASK_CALIB_START;
+	hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
+	PHY_DEBUG(("[CAL]    MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
+}
+
 /* 20060612.1.a 20060718.1 Modify */
-static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
+u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
 						   s32 a_2_threshold,
 						   s32 b_2_threshold)
 {
@@ -434,8 +711,7 @@ static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
 	loop = LOOP_TIMES;
 
 	while (loop > 0) {
-		PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n",
-				   (LOOP_TIMES-loop+1)));
+		PHY_DEBUG(("[CAL] [%d.] <_tx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
 
 		iqcal_tone_i_avg = 0;
 		iqcal_tone_q_avg = 0;
@@ -443,8 +719,8 @@ static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
 			return 0;
 		for (capture_time = 0; capture_time < 10; capture_time++) {
 			/*
-			 * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start"
-			 *    to 0x1 to enable "IQ calibration Mode II"
+			 * a. Set iqcal_mode[1:0] to 0x2 and set "calib_start" to 0x1 to
+			 *    enable "IQ calibration Mode II"
 			 */
 			reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
 			reg_mode_ctrl &= ~MASK_IQCAL_MODE;
@@ -473,8 +749,8 @@ static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
 			PHY_DEBUG(("[CAL]    MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
 
 			/*
-			 * d. Set iqcal_mode[1:0] to 0x3 and set "calib_start"
-			 *    to 0x1 to enable "IQ calibration Mode II"
+			 * d. Set iqcal_mode[1:0] to 0x3 and set "calib_start" to 0x1 to
+			 *    enable "IQ calibration Mode II"
 			 */
 			/* hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &val); */
 			hw_get_dxx_reg(phw_data, REG_MODE_CTRL, &reg_mode_ctrl);
@@ -490,7 +766,7 @@ static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
 			iqcal_tone_i = _s13_to_s32(val & 0x00001FFF);
 			iqcal_tone_q = _s13_to_s32((val & 0x03FFE000) >> 13);
 			PHY_DEBUG(("[CAL]    ** iqcal_tone_i = %d, iqcal_tone_q = %d\n",
-					   iqcal_tone_i, iqcal_tone_q));
+			iqcal_tone_i, iqcal_tone_q));
 			if (capture_time == 0)
 				continue;
 			else {
@@ -679,7 +955,7 @@ static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
 	return 1;
 }
 
-static void _tx_iq_calibration_winbond(struct hw_data *phw_data)
+void _tx_iq_calibration_winbond(struct hw_data *phw_data)
 {
 	u32     reg_agc_ctrl3;
 #ifdef _DEBUG
@@ -825,7 +1101,7 @@ static void _tx_iq_calibration_winbond(struct hw_data *phw_data)
 }
 
 /*****************************************************/
-static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
+u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
 {
 	u32     reg_mode_ctrl;
 	s32     iqcal_tone_i;
@@ -870,8 +1146,7 @@ static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor,
 	/* for (loop = 0; loop < LOOP_TIMES; loop++) */
 	loop = LOOP_TIMES;
 	while (loop > 0) {
-		PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n",
-				   (LOOP_TIMES-loop+1)));
+		PHY_DEBUG(("[CAL] [%d.] <_rx_iq_calibration_loop>\n", (LOOP_TIMES-loop+1)));
 		iqcal_tone_i_avg = 0;
 		iqcal_tone_q_avg = 0;
 		iqcal_image_i_avg = 0;
@@ -924,13 +1199,13 @@ static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor,
 
 		/* d. */
 		rot_tone_i_b = (iqcal_tone_i * iqcal_tone_i +
-					iqcal_tone_q * iqcal_tone_q) / 1024;
+						iqcal_tone_q * iqcal_tone_q) / 1024;
 		rot_tone_q_b = (iqcal_tone_i * iqcal_tone_q * (-1) +
-					iqcal_tone_q * iqcal_tone_i) / 1024;
+						iqcal_tone_q * iqcal_tone_i) / 1024;
 		rot_image_i_b = (iqcal_image_i * iqcal_tone_i -
-					iqcal_image_q * iqcal_tone_q) / 1024;
+						 iqcal_image_q * iqcal_tone_q) / 1024;
 		rot_image_q_b = (iqcal_image_i * iqcal_tone_q +
-					iqcal_image_q * iqcal_tone_i) / 1024;
+						 iqcal_image_q * iqcal_tone_i) / 1024;
 
 		PHY_DEBUG(("[CAL]    ** rot_tone_i_b  = %d\n", rot_tone_i_b));
 		PHY_DEBUG(("[CAL]    ** rot_tone_q_b  = %d\n", rot_tone_q_b));
@@ -950,10 +1225,8 @@ static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor,
 		b_2 = (rot_image_q_b * 32768) / rot_tone_i_b -
 			phw_data->iq_rsdl_phase_tx_d2;
 
-		PHY_DEBUG(("[CAL]    ** iq_rsdl_gain_tx_d2 = %d\n",
-			   phw_data->iq_rsdl_gain_tx_d2));
-		PHY_DEBUG(("[CAL]    ** iq_rsdl_phase_tx_d2= %d\n",
-			   phw_data->iq_rsdl_phase_tx_d2));
+		PHY_DEBUG(("[CAL]    ** iq_rsdl_gain_tx_d2 = %d\n", phw_data->iq_rsdl_gain_tx_d2));
+		PHY_DEBUG(("[CAL]    ** iq_rsdl_phase_tx_d2= %d\n", phw_data->iq_rsdl_phase_tx_d2));
 		PHY_DEBUG(("[CAL]    ***** EPSILON/2 = %d\n", a_2));
 		PHY_DEBUG(("[CAL]    ***** THETA/2   = %d\n", b_2));
 
@@ -999,8 +1272,7 @@ static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor,
 
 		/* e. */
 		pwr_tone = (iqcal_tone_i*iqcal_tone_i + iqcal_tone_q*iqcal_tone_q);
-		pwr_image = (iqcal_image_i*iqcal_image_i +
-			     iqcal_image_q*iqcal_image_q)*factor;
+		pwr_image = (iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q)*factor;
 
 		PHY_DEBUG(("[CAL]    ** pwr_tone  = %d\n", pwr_tone));
 		PHY_DEBUG(("[CAL]    ** pwr_image  = %d\n", pwr_image));
@@ -1099,7 +1371,7 @@ static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor,
 /*************************************************/
 
 /***************************************************************/
-static void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
+void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
 {
 /* figo 20050523 marked this flag for can't compile for release */
 #ifdef _DEBUG
@@ -1297,8 +1569,7 @@ unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
 
 		sqsum = iqcal_tone_i0*iqcal_tone_i0 + iqcal_tone_q0*iqcal_tone_q0;
 		iq_mag_0_tx = (s32) _sqrt(sqsum);
-		PHY_DEBUG(("[CAL]    ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n",
-			   iq_mag_0_tx));
+		PHY_DEBUG(("[CAL]    ** auto_adjust_txvga_for_iq_mag_0_tx=%d\n", iq_mag_0_tx));
 
 		if (iq_mag_0_tx >= 700 && iq_mag_0_tx <= 1750)
 			break;
diff --git a/drivers/staging/winbond/reg.c b/drivers/staging/winbond/reg.c
index 5fd4c4a..75b7752 100644
--- a/drivers/staging/winbond/reg.c
+++ b/drivers/staging/winbond/reg.c
@@ -43,7 +43,7 @@
  */
 
 /* MAX2825 (pure b/g) */
-static u32 max2825_rf_data[] = {
+u32 max2825_rf_data[] = {
 	(0x00<<18) | 0x000a2,
 	(0x01<<18) | 0x21cc0,
 	(0x02<<18) | 0x13806,
@@ -59,7 +59,7 @@ static u32 max2825_rf_data[] = {
 	(0x0C<<18) | 0x0c100   /* 11a: 0x0c300, 11g: 0x0c100 */
 };
 
-static u32 max2825_channel_data_24[][3] = {
+u32 max2825_channel_data_24[][3] = {
 	{(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 01 */
 	{(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 02 */
 	{(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 03 */
@@ -76,11 +76,11 @@ static u32 max2825_channel_data_24[][3] = {
 	{(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}  /* channel 14 (2484MHz) */
 };
 
-static u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
+u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
 
 /* ========================================== */
 /* MAX2827 (a/b/g) */
-static u32 max2827_rf_data[] = {
+u32 max2827_rf_data[] = {
 	(0x00 << 18) | 0x000a2,
 	(0x01 << 18) | 0x21cc0,
 	(0x02 << 18) | 0x13806,
@@ -96,7 +96,7 @@ static u32 max2827_rf_data[] = {
 	(0x0C << 18) | 0x0c100   /* 11a: 0x0c300, 11g: 0x0c100 */
 };
 
-static u32 max2827_channel_data_24[][3] = {
+u32 max2827_channel_data_24[][3] = {
 	{(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
 	{(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
 	{(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
@@ -113,7 +113,7 @@ static u32 max2827_channel_data_24[][3] = {
 	{(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}  /* channel 14 (2484MHz) */
 };
 
-static u32 max2827_channel_data_50[][3] = {
+u32 max2827_channel_data_50[][3] = {
 	{(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 36 */
 	{(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 40 */
 	{(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}, /* channel 44 */
@@ -124,12 +124,12 @@ static u32 max2827_channel_data_50[][3] = {
 	{(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}  /* channel 64 */
 };
 
-static u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100};
-static u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300};
+u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100};
+u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300};
 
 /* ======================================================= */
 /* MAX2828 (a/b/g) */
-static u32 max2828_rf_data[] = {
+u32 max2828_rf_data[] = {
 	(0x00 << 18) | 0x000a2,
 	(0x01 << 18) | 0x21cc0,
 	(0x02 << 18) | 0x13806,
@@ -145,7 +145,7 @@ static u32 max2828_rf_data[] = {
 	(0x0C << 18) | 0x0c100   /* 11a: 0x0c300, 11g: 0x0c100 */
 };
 
-static u32 max2828_channel_data_24[][3] = {
+u32 max2828_channel_data_24[][3] = {
 	{(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
 	{(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
 	{(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
@@ -162,7 +162,7 @@ static u32 max2828_channel_data_24[][3] = {
 	{(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}  /* channel 14 (2484MHz) */
 };
 
-static u32 max2828_channel_data_50[][3] = {
+u32 max2828_channel_data_50[][3] = {
 	{(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 36 */
 	{(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 40 */
 	{(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 44 */
@@ -173,12 +173,12 @@ static u32 max2828_channel_data_50[][3] = {
 	{(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}  /* channel 64 */
 };
 
-static u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
-static u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
+u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
+u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
 
 /* ========================================================== */
 /* MAX2829 (a/b/g) */
-static u32 max2829_rf_data[] = {
+u32 max2829_rf_data[] = {
 	(0x00 << 18) | 0x000a2,
 	(0x01 << 18) | 0x23520,
 	(0x02 << 18) | 0x13802,
@@ -194,7 +194,7 @@ static u32 max2829_rf_data[] = {
 	(0x0C << 18) | 0x0F300 /* TXVGA=51, (MAX-6 dB) */
 };
 
-static u32 max2829_channel_data_24[][3] = {
+u32 max2829_channel_data_24[][3] = {
 	{(3 << 18) | 0x30142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6},  /* 01 (2412MHz) */
 	{(3 << 18) | 0x32141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6},  /* 02 (2417MHz) */
 	{(3 << 18) | 0x32143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6},  /* 03 (2422MHz) */
@@ -211,7 +211,7 @@ static u32 max2829_channel_data_24[][3] = {
 	{(3 << 18) | 0x32941, (4 << 18) | 0x09999, (5 << 18) | 0x289C6},  /* 14 (2484MHz) */
 };
 
-static u32 max2829_channel_data_50[][4] = {
+u32 max2829_channel_data_50[][4] = {
 	{36, (3 << 18) | 0x33cc3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 36 (5.180GHz) */
 	{40, (3 << 18) | 0x302c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 40 (5.200GHz) */
 	{44, (3 << 18) | 0x302c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 44 (5.220GHz) */
@@ -296,6 +296,51 @@ static u32 max2829_channel_data_50[][4] = {
  * 0x0c 0x0c000
  * ====================================================================
  */
+u32 maxim_317_rf_data[] = {
+	(0x00 << 18) | 0x000a2,
+	(0x01 << 18) | 0x214c0,
+	(0x02 << 18) | 0x13802,
+	(0x03 << 18) | 0x30143,
+	(0x04 << 18) | 0x0accc,
+	(0x05 << 18) | 0x28986,
+	(0x06 << 18) | 0x18008,
+	(0x07 << 18) | 0x38400,
+	(0x08 << 18) | 0x05108,
+	(0x09 << 18) | 0x27ff8,
+	(0x0A << 18) | 0x14000,
+	(0x0B << 18) | 0x37f99,
+	(0x0C << 18) | 0x0c000
+};
+
+u32 maxim_317_channel_data_24[][3] = {
+	{(0x03 << 18) | 0x30143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 01 */
+	{(0x03 << 18) | 0x32140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 02 */
+	{(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 03 */
+	{(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 04 */
+	{(0x03 << 18) | 0x31140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 05 */
+	{(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 06 */
+	{(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 07 */
+	{(0x03 << 18) | 0x33140, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 08 */
+	{(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 09 */
+	{(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}, /* channe1 10 */
+	{(0x03 << 18) | 0x30940, (0x04 << 18) | 0x09111, (0x05 << 18) | 0x28986}, /* channe1 11 */
+	{(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0bbbb, (0x05 << 18) | 0x28986}, /* channe1 12 */
+	{(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x28986}  /* channe1 13 */
+};
+
+u32 maxim_317_channel_data_50[][3] = {
+	{(0x03 << 18) | 0x33cc0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a986}, /* channel 36 */
+	{(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a986}, /* channel 40 */
+	{(0x03 << 18) | 0x302c3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a986}, /* channel 44 */
+	{(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09666, (0x05 << 18) | 0x2a986}, /* channel 48 */
+	{(0x03 << 18) | 0x312c2, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2a986}, /* channel 52 */
+	{(0x03 << 18) | 0x332c0, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2a99e}, /* channel 56 */
+	{(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2a99e}, /* channel 60 */
+	{(0x03 << 18) | 0x30ac3, (0x04 << 18) | 0x0accc, (0x05 << 18) | 0x2a99e}  /* channel 64 */
+};
+
+u32 maxim_317_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
+u32 maxim_317_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
 
 /*
  * ===================================================================
@@ -343,7 +388,7 @@ static u32 max2829_channel_data_50[][4] = {
  * 0x0f 0xf00a0 ; Restore Initial Setting
  * ==================================================================
  */
-static u32 al2230_rf_data[] = {
+u32 al2230_rf_data[] = {
 	(0x00 << 20) | 0x09EFC,
 	(0x01 << 20) | 0x8CCCC,
 	(0x02 << 20) | 0x40058,
@@ -361,7 +406,7 @@ static u32 al2230_rf_data[] = {
 	(0x0F << 20) | 0xF01A0
 };
 
-static u32 al2230s_rf_data[] = {
+u32 al2230s_rf_data[] = {
 	(0x00 << 20) | 0x09EFC,
 	(0x01 << 20) | 0x8CCCC,
 	(0x02 << 20) | 0x40058,
@@ -379,7 +424,7 @@ static u32 al2230s_rf_data[] = {
 	(0x0F << 20) | 0xF01A0
 };
 
-static u32 al2230_channel_data_24[][2] = {
+u32 al2230_channel_data_24[][2] = {
 	{(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 01 */
 	{(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 02 */
 	{(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 03 */
@@ -401,7 +446,7 @@ static u32 al2230_channel_data_24[][2] = {
 #define AIROHA_TXVGA_MIDDLE_INDEX	12	/* Index for 0x96602 */
 #define AIROHA_TXVGA_HIGH_INDEX		8	/* Index for 0x97602 1.0.24.0 1.0.28.0 */
 
-static u32 al2230_txvga_data[][2] = {
+u32 al2230_txvga_data[][2] = {
 	/* value , index */
 	{0x090202, 0},
 	{0x094202, 2},
@@ -452,7 +497,7 @@ static u32 al2230_txvga_data[][2] = {
  */
 
 /* channel independent registers: */
-static u32 al7230_rf_data_24[]	= {
+u32 al7230_rf_data_24[]	= {
 	(0x00 << 24) | 0x003790,
 	(0x01 << 24) | 0x133331,
 	(0x02 << 24) | 0x841FF2,
@@ -471,7 +516,7 @@ static u32 al7230_rf_data_24[]	= {
 	(0x0F << 24) | 0x1ABA8F
 };
 
-static u32 al7230_channel_data_24[][2] = {
+u32 al7230_channel_data_24[][2] = {
 	{(0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331}, /* channe1 01 */
 	{(0x00 << 24) | 0x003790, (0x01 << 24) | 0x1B3331}, /* channe1 02 */
 	{(0x00 << 24) | 0x003790, (0x01 << 24) | 0x033331}, /* channe1 03 */
@@ -489,7 +534,7 @@ static u32 al7230_channel_data_24[][2] = {
 };
 
 /* channel independent registers: */
-static u32 al7230_rf_data_50[]	= {
+u32 al7230_rf_data_50[]	= {
 	(0x00 << 24) | 0x0FF520,
 	(0x01 << 24) | 0x000001,
 	(0x02 << 24) | 0x451FE2,
@@ -508,7 +553,7 @@ static u32 al7230_rf_data_50[]	= {
 	(0x0F << 24) | 0x12BACF  /* 5Ghz default state */
 };
 
-static u32 al7230_channel_data_5[][4] = {
+u32 al7230_channel_data_5[][4] = {
 	/* channel dependent registers: 0x00, 0x01 and 0x04 */
 	/* 11J =========== */
 	{184, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 184 */
@@ -558,7 +603,7 @@ static u32 al7230_channel_data_5[][4] = {
  */
 
 /* TXVGA Mapping Table <=== Register 0x0B */
-static u32 al7230_txvga_data[][2] = {
+u32 al7230_txvga_data[][2] = {
 	{0x08040B, 0}, /* TXVGA = 0; */
 	{0x08041B, 1}, /* TXVGA = 1; */
 	{0x08042B, 2}, /* TXVGA = 2; */
@@ -630,7 +675,7 @@ static u32 al7230_txvga_data[][2] = {
  * W89RF242 RFIC SPI programming initial data
  * Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
  */
-static u32 w89rf242_rf_data[] = {
+u32 w89rf242_rf_data[] = {
 	(0x00 << 24) | 0xF86100, /* 3E184; MODA  (0x00) -- Normal mode ; calibration off */
 	(0x01 << 24) | 0xEFFFC2, /* 3BFFF; MODB  (0x01) -- turn off RSSI, and other circuits are turned on */
 	(0x02 << 24) | 0x102504, /* 04094; FSET  (0x02) -- default 20MHz crystal ; Icmp=1.5mA */
@@ -651,7 +696,7 @@ static u32 w89rf242_rf_data[] = {
 	(0x12 << 24) | 0x000024  /* TMODC (0x12) -- Turn OFF Temperature sensor */
 };
 
-static u32 w89rf242_channel_data_24[][2] = {
+u32 w89rf242_channel_data_24[][2] = {
 	{(0x03 << 24) | 0x025B06, (0x04 << 24) | 0x080408}, /* channe1 01 */
 	{(0x03 << 24) | 0x025C46, (0x04 << 24) | 0x080408}, /* channe1 02 */
 	{(0x03 << 24) | 0x025D86, (0x04 << 24) | 0x080408}, /* channe1 03 */
@@ -668,7 +713,9 @@ static u32 w89rf242_channel_data_24[][2] = {
 	{(0x03 << 24) | 0x026D06, (0x04 << 24) | 0x080408}  /* channe1 14 */
 };
 
-static u32 w89rf242_txvga_old_mapping[][2] = {
+u32 w89rf242_power_data_24[] = {(0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A, (0x05 << 24) | 0x24C48A};
+
+u32 w89rf242_txvga_old_mapping[][2] = {
 	{0, 0} , /* New <-> Old */
 	{1, 1} ,
 	{2, 2} ,
@@ -691,7 +738,7 @@ static u32 w89rf242_txvga_old_mapping[][2] = {
 	{34, 19},
 };
 
-static u32 w89rf242_txvga_data[][5] = {
+u32 w89rf242_txvga_data[][5] = {
 	/* low gain mode */
 	{(0x05 << 24) | 0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131}, /* min gain */
 	{(0x05 << 24) | 0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131},
@@ -873,7 +920,7 @@ void Uxx_power_on_procedure(struct hw_data *pHwData)
 	Wb35Reg_WriteSync(pHwData, 0x03f8, 0x7ff);
 }
 
-static void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp,
+static void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp, 
 					char number)
 {
 	u8	i;
@@ -883,7 +930,7 @@ static void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp,
 	}
 }
 
-static void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp,
+static void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp, 
 					char number)
 {
 	u8	i;
@@ -1041,7 +1088,7 @@ void RFSynthesizer_initial(struct hw_data *pHwData)
 		msleep(5);
 
 		ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20);
-		Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
+		Wb35Reg_WriteSync(pHwData, 0x0864, ltmp) ;
 
 		Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
 		pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
@@ -1573,13 +1620,13 @@ void BBProcessor_initial(struct hw_data *pHwData)
 		reg->SQ3_filter[i] = 0x2f; /* half of Bit 0 ~ 6 */
 }
 
-static inline void set_tx_power_per_channel_max2829(struct hw_data *pHwData,
+static inline void set_tx_power_per_channel_max2829(struct hw_data *pHwData,  
 						struct chan_info Channel)
 {
 	RFSynthesizer_SetPowerIndex(pHwData, 100);
 }
 
-static void set_tx_power_per_channel_al2230(struct hw_data *pHwData,
+static void set_tx_power_per_channel_al2230(struct hw_data *pHwData,  
 					struct chan_info Channel)
 {
 	u8	index = 100;
@@ -1589,7 +1636,7 @@ static void set_tx_power_per_channel_al2230(struct hw_data *pHwData,
 	RFSynthesizer_SetPowerIndex(pHwData, index);
 }
 
-static void set_tx_power_per_channel_al7230(struct hw_data *pHwData,
+static void set_tx_power_per_channel_al7230(struct hw_data *pHwData,  
 					struct chan_info Channel)
 {
 	u8	i, index = 100;
@@ -1613,7 +1660,7 @@ static void set_tx_power_per_channel_al7230(struct hw_data *pHwData,
 	RFSynthesizer_SetPowerIndex(pHwData, index);
 }
 
-static void set_tx_power_per_channel_wb242(struct hw_data *pHwData,
+static void set_tx_power_per_channel_wb242(struct hw_data *pHwData,  
 					struct chan_info Channel)
 {
 	u8	index = 100;
@@ -2049,7 +2096,7 @@ void Mxx_initial(struct hw_data *pHwData)
 	pltmp[5] = reg->M38_MacControl;
 
 	/* M3C */
-	tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST;
+	tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST ;
 	reg->M3C_MacControl = tmp;
 	pltmp[6] = tmp;
 
diff --git a/drivers/staging/winbond/wb35tx.c b/drivers/staging/winbond/wb35tx.c
index 708c5b0..30a77cc 100644
--- a/drivers/staging/winbond/wb35tx.c
+++ b/drivers/staging/winbond/wb35tx.c
@@ -180,7 +180,7 @@ void Wb35Tx_CurrentTime(struct wbsoft_priv *adapter, u32 TimeCount)
 {
 	struct hw_data *pHwData = &adapter->sHwData;
 	struct wb35_tx *pWb35Tx = &pHwData->Wb35Tx;
-	bool Trigger = false;
+	unsigned char Trigger = false;
 
 	if (pWb35Tx->TxTimer > TimeCount)
 		Trigger = true;
diff --git a/drivers/staging/winbond/wbusb.c b/drivers/staging/winbond/wbusb.c
index 07891a3..3fa1ae4 100644
--- a/drivers/staging/winbond/wbusb.c
+++ b/drivers/staging/winbond/wbusb.c
@@ -122,16 +122,16 @@ static void wbsoft_tx(struct ieee80211_hw *dev,
 {
 	struct wbsoft_priv *priv = dev->priv;
 
-	if (priv->sMlmeFrame.is_in_used != PACKET_FREE_TO_USE) {
+	if (priv->sMlmeFrame.IsInUsed != PACKET_FREE_TO_USE) {
 		priv->sMlmeFrame.wNumTxMMPDUDiscarded++;
 		kfree_skb(skb);
 		return;
 	}
 
-	priv->sMlmeFrame.is_in_used = PACKET_COME_FROM_MLME;
+	priv->sMlmeFrame.IsInUsed = PACKET_COME_FROM_MLME;
 
 	priv->sMlmeFrame.pMMPDU		= skb->data;
-	priv->sMlmeFrame.data_type	= FRAME_TYPE_802_11_MANAGEMENT;
+	priv->sMlmeFrame.DataType	= FRAME_TYPE_802_11_MANAGEMENT;
 	priv->sMlmeFrame.len		= skb->len;
 	priv->sMlmeFrame.wNumTxMMPDU++;