diff options
| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2014-03-24 10:55:10 (GMT) |
|---|---|---|
| committer | Jose Rivera <German.Rivera@freescale.com> | 2014-03-25 17:05:48 (GMT) |
| commit | 2bd36cbf3554ccf06dab56ec0249837ecab7356f (patch) | |
| tree | 7b2709e36871da92f653bf291ef32e19f64304a6 /drivers/tty | |
| parent | 3be02f7adc1646d12e1d95c7036209e74b9e9ccb (diff) | |
| download | linux-fsl-qoriq-2bd36cbf3554ccf06dab56ec0249837ecab7356f.tar.xz | |
Add 64byte FiFo mode UART support for FSL platforms
T1040 FSL SoC has new version of UART controller which
can support 64byte FiFo. Add suuport to enable 64byte FiFO mode
-FCR[EN64] needs to be programmed to 1 to enable it.
-Also, when FCR[EN64]==1, RTL bits to be used as below
to define various Receive Trigger Levels:
-FCR[RTL] = 00 1 byte
-FCR[RTL] = 01 16 bytes
-FCR[RTL] = 10 32 bytes
-FCR[RTL] = 11 56 bytes
-tx_loadsz is set tp 32bytes, As some issues are observed with
64-byte mode which looks to be Si issue.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Change-Id: I0b32f3230bd1c9674a2e85cc4e5a16869dbaa9af
Reviewed-on: http://git.am.freescale.net:8181/10215
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/8250/8250_core.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index e33d38c..997dc4f 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c @@ -323,6 +323,14 @@ static const struct serial8250_config uart_config[] = { .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, .flags = UART_CAP_FIFO | UART_CAP_AFE, }, + [PORT_16550A_FSL64] = { + .name = "16550A_FSL64", + .fifo_size = 64, + .tx_loadsz = 32, + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | + UART_FCR7_64BYTE, + .flags = UART_CAP_FIFO, + }, }; /* Uart divisor latch read */ @@ -899,7 +907,17 @@ static void autoconfig_16550a(struct uart_8250_port *up) up->port.type = PORT_16650; up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; } else { - DEBUG_AUTOCONF("Motorola 8xxx DUART "); + serial_out(up, UART_LCR, 0); + serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | + UART_FCR7_64BYTE); + status1 = serial_in(up, UART_IIR) >> 5; + serial_out(up, UART_FCR, 0); + serial_out(up, UART_LCR, 0); + + if (status1 == 7) + up->port.type = PORT_16550A_FSL64; + else + DEBUG_AUTOCONF("Motorola 8xxx DUART "); } serial_out(up, UART_EFR, 0); return; |