diff options
| author | Felipe Balbi <balbi@ti.com> | 2011-09-30 07:58:50 (GMT) |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-04 17:25:56 (GMT) |
| commit | aabb70752361a8b8ca44142a942a5bd133c4d304 (patch) | |
| tree | ddc6da1f1a031834d9478cc85301c2d796da389a /drivers/usb/dwc3/gadget.c | |
| parent | 26ceca9750260997ab82bb84dac122de1e441658 (diff) | |
| download | linux-fsl-qoriq-aabb70752361a8b8ca44142a942a5bd133c4d304.tar.xz | |
usb: dwc3: gadget: allow clock gating to work
The dwc3 core has internal clock gating support.
Let's allow that to happen by clearing the disable
bit in GCTL register.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/usb/dwc3/gadget.c')
| -rw-r--r-- | drivers/usb/dwc3/gadget.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 8d85023..fd1ac4d 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1164,6 +1164,14 @@ static int dwc3_gadget_start(struct usb_gadget *g, reg &= ~DWC3_GCTL_DISSCRAMBLE; reg |= DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE); + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams0)) { + case DWC3_GHWPARAMS1_EN_PWROPT_CLK: + reg &= ~DWC3_GCTL_DSBLCLKGTNG; + break; + default: + dev_dbg(dwc->dev, "No power optimization available\n"); + } + /* * WORKAROUND: DWC3 revisions <1.90a have a bug * when The device fails to connect at SuperSpeed |