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authorJ. German Rivera <Jose.G.Rivera@freescale.com>2013-08-30 19:18:38 (GMT)
committerJ. German Rivera <German.Rivera@freescale.com>2013-08-30 19:18:38 (GMT)
commit63dd6020dd279c1860363450a38e890a3f17ef50 (patch)
tree22a55418f0e18b78e14cd3a2f516b8acea4c8f3a /drivers/usb
parent994a9d7b30088adf0d931c0287ce95c0b5000620 (diff)
parentfc3e003a3733cac43416b27536b4179bfc82718d (diff)
downloadlinux-fsl-qoriq-63dd6020dd279c1860363450a38e890a3f17ef50.tar.xz
Merge branch 'sdk-kernel-3.8'
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/host/ehci-fsl.c51
-rw-r--r--drivers/usb/host/ehci-fsl.h3
2 files changed, 46 insertions, 8 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index e247c3d..73418c5 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -52,6 +52,46 @@ struct ehci_fsl {
unsigned hcd_add:1;
};
+static bool usb_phy_clk_valid(struct usb_hcd *hcd,
+ enum fsl_usb2_phy_modes phy_mode)
+{
+ void __iomem *non_ehci = hcd->regs;
+ struct device *dev = hcd->self.controller;
+ struct fsl_usb2_platform_data *pdata = dev->platform_data;
+ bool ret = true;
+ int retry = UTMI_PHY_CLK_VALID_CHK_RETRY;
+
+ if (phy_mode == FSL_USB2_PHY_ULPI) {
+ /* check PHY_CLK_VALID to get phy clk valid */
+ if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
+ PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
+ in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
+ ret = false;
+ }
+ } else if (phy_mode == FSL_USB2_PHY_UTMI) {
+ if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) {
+ ret = false;
+ if (pdata->controller_ver < FSL_USB_VER_2_4) {
+ while (retry--) {
+ clrbits32(non_ehci + FSL_SOC_USB_CTRL,
+ CTRL_UTMI_PHY_EN);
+ setbits32(non_ehci + FSL_SOC_USB_CTRL,
+ CTRL_UTMI_PHY_EN);
+ /* delay required for Clk to appear */
+ mdelay(FSL_UTMI_PHY_DLY);
+ if ((in_be32(non_ehci +
+ FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) {
+ ret = true;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ return ret;
+}
+
static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
@@ -325,14 +365,9 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
}
if (pdata->have_sysif_regs && pdata->controller_ver &&
- (phy_mode == FSL_USB2_PHY_ULPI)) {
- /* check PHY_CLK_VALID to get phy clk valid */
- if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
- PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
- in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
- printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
- return -EINVAL;
- }
+ !usb_phy_clk_valid(hcd, phy_mode)) {
+ printk(KERN_ERR "fsl-ehci: USB PHY clock invalid\n");
+ return -EINVAL;
}
ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index dbd292e..a032358 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -62,4 +62,7 @@
#define UTMI_PHY_EN (1<<9)
#define ULPI_PHY_CLK_SEL (1<<10)
#define PHY_CLK_VALID (1<<17)
+
+/* Retry count for checking UTMI PHY CLK validity */
+#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
#endif /* _EHCI_FSL_H */