diff options
| author | Nikhil Badola <nikhil.badola@freescale.com> | 2014-06-02 13:08:47 (GMT) |
|---|---|---|
| committer | Matthew Weigel <Matthew.Weigel@freescale.com> | 2014-12-11 18:38:23 (GMT) |
| commit | e5ca81cdc3ad921bd038d653d82b607c2f2aabe8 (patch) | |
| tree | cad764bbc3ec6d76092481d45e8dc330416b5142 /drivers/usb | |
| parent | 39ee2e9601e8b73aa6f11198fc65ab160e1c4d26 (diff) | |
| download | linux-fsl-qoriq-e5ca81cdc3ad921bd038d653d82b607c2f2aabe8.tar.xz | |
drivers/usb : Port USB EHCI Gadget driver for LS102XA
Change raw read/write accessors to ioread/writebe32 for big endian registers
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: I75e181fc235f40aba7aa0d9db8f18c0783b04f82
Reviewed-on: http://git.am.freescale.net:8181/21818
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/gadget/fsl_udc_core.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c index c540dfa..ef4a00f 100644 --- a/drivers/usb/gadget/fsl_udc_core.c +++ b/drivers/usb/gadget/fsl_udc_core.c @@ -245,10 +245,10 @@ static int dr_controller_setup(struct fsl_udc *udc) if (udc->pdata->have_sysif_regs) { if (udc->pdata->controller_ver) { /* controller version 1.6 or above */ - ctrl = __raw_readl(&usb_sys_regs->control); + ctrl = ioread32be(&usb_sys_regs->control); ctrl &= ~USB_CTRL_UTMI_PHY_EN; ctrl |= USB_CTRL_USB_EN; - __raw_writel(ctrl, &usb_sys_regs->control); + iowrite32be(ctrl, &usb_sys_regs->control); } } portctrl |= PORTSCX_PTS_ULPI; @@ -260,10 +260,10 @@ static int dr_controller_setup(struct fsl_udc *udc) if (udc->pdata->have_sysif_regs) { if (udc->pdata->controller_ver) { /* controller version 1.6 or above */ - ctrl = __raw_readl(&usb_sys_regs->control); + ctrl = ioread32be(&usb_sys_regs->control); ctrl |= (USB_CTRL_UTMI_PHY_EN | USB_CTRL_USB_EN); - __raw_writel(ctrl, &usb_sys_regs->control); + iowrite32be(ctrl, &usb_sys_regs->control); mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to become stable - 10ms*/ } @@ -329,22 +329,22 @@ static int dr_controller_setup(struct fsl_udc *udc) /* Config control enable i/o output, cpu endian register */ #ifndef CONFIG_ARCH_MXC if (udc->pdata->have_sysif_regs) { - ctrl = __raw_readl(&usb_sys_regs->control); + ctrl = ioread32be(&usb_sys_regs->control); ctrl |= USB_CTRL_IOENB; - __raw_writel(ctrl, &usb_sys_regs->control); + iowrite32be(ctrl, &usb_sys_regs->control); } #endif -#if !defined(CONFIG_NOT_COHERENT_CACHE) +#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) /* Turn on cache snooping hardware, since some PowerPC platforms * wholly rely on hardware to deal with cache coherent. */ if (udc->pdata->have_sysif_regs) { /* Setup Snooping for all the 4GB space */ tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */ - __raw_writel(tmp, &usb_sys_regs->snoop1); + iowrite32be(tmp, &usb_sys_regs->snoop1); tmp |= 0x80000000; /* starts from 0x8000000, size 2G */ - __raw_writel(tmp, &usb_sys_regs->snoop2); + iowrite32be(tmp, &usb_sys_regs->snoop2); } #endif |