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authorChandrabhanu Mahapatra <cmahapatra@ti.com>2012-04-23 06:46:50 (GMT)
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-05-03 13:13:01 (GMT)
commit8b53d9911982794b3f6d5513741495c3f70962cd (patch)
tree2932bf95e14f4d890704983918d19e4a482593f7 /drivers/video/omap2/dss/dss.h
parent7faa92339bbb1e6b9a80983b206642517327eb75 (diff)
downloadlinux-fsl-qoriq-8b53d9911982794b3f6d5513741495c3f70962cd.tar.xz
OMAPDSS: DISPC: Correct DISPC functional clock usage
DISPC_FCLK is incorrectly used as functional clock of DISPC in scaling calculations. So, DISPC_CORE_CLK replaces as functional clock of DISPC. DISPC_CORE_CLK is derived from DISPC_FCLK divided by an independent DISPC divisor LCD. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/dss.h')
-rw-r--r--drivers/video/omap2/dss/dss.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index 1dc336b..5ca67f1 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -448,6 +448,7 @@ void dispc_mgr_set_pol_freq(enum omap_channel channel,
enum omap_panel_config config, u8 acbi, u8 acb);
unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
+unsigned long dispc_core_clk_rate(void);
int dispc_mgr_set_clock_div(enum omap_channel channel,
struct dispc_clock_info *cinfo);
int dispc_mgr_get_clock_div(enum omap_channel channel,