diff options
| author | Jianwei Wang <b52261@freescale.com> | 2015-03-05 06:33:54 (GMT) |
|---|---|---|
| committer | Zhengxiong Jin <Jason.Jin@freescale.com> | 2015-03-06 06:05:51 (GMT) |
| commit | c5f2088fefec884486617c0efeb3b92e75b8d8c7 (patch) | |
| tree | 6c038685ea95f8c25526eecaaadd4305ac3a3be1 /drivers/video | |
| parent | 42daf8575d06ae4f2280fa49b2a80b50dab92da1 (diff) | |
| download | linux-fsl-qoriq-c5f2088fefec884486617c0efeb3b92e75b8d8c7.tar.xz | |
Fix deep sleep stops working bug
For pixel clock is not disable when suspend, deep sleep stops
working. Disable pixel clock when suspend and enable when resume.
Signed-off-by: Jianwei Wang <b52261@freescale.com>
Change-Id: Icb9b04afa4fefbf6be70160faddf34fc81639321
Reviewed-on: http://git.am.freescale.net:8181/31997
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yao Yuan <yao.yuan@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Diffstat (limited to 'drivers/video')
| -rw-r--r-- | drivers/video/fsl-dcu-fb.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/video/fsl-dcu-fb.c b/drivers/video/fsl-dcu-fb.c index 3fc0b79..81a8541 100644 --- a/drivers/video/fsl-dcu-fb.c +++ b/drivers/video/fsl-dcu-fb.c @@ -138,6 +138,10 @@ #define TCON_CTRL1 0x00 #define TCON_BYPASS_ENABLE BIT(29) +#define SCFG_PIXCLKCR 0x28 +#define PXCKEN BIT(31) +#define PXCK_DISABLE 0 + #define MFB_SET_ALPHA _IOW('M', 0, __u8) #define MFB_GET_ALPHA _IOR('M', 0, __u8) #define MFB_SET_LAYER _IOW('M', 4, struct layer_display_offset) @@ -1184,6 +1188,7 @@ static int fsl_dcu_suspend(struct device *dev) { struct dcu_fb_data *dcufb = dev_get_drvdata(dev); + regmap_write(dcufb->scfg_regmap, SCFG_PIXCLKCR, PXCK_DISABLE); regcache_cache_only(dcufb->regmap, true); regcache_mark_dirty(dcufb->regmap); clk_disable_unprepare(dcufb->clk); @@ -1223,6 +1228,7 @@ static int fsl_dcu_resume(struct device *dev) reset_total_layers(np, dcufb); regcache_cache_only(dcufb->regmap, false); regcache_sync(dcufb->regmap); + regmap_write(dcufb->scfg_regmap, SCFG_PIXCLKCR, PXCKEN); return 0; } |