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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-18 14:25:08 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-18 18:43:25 (GMT) |
| commit | 750eb99e0ec12f9a13446284d493d35a60866624 (patch) | |
| tree | 9d48d26fee453c547f747d2081b1ea90294c46ec /drivers | |
| parent | 16995a9fe140802c026c2ce17bf7e232f86d57ab (diff) | |
| download | linux-fsl-qoriq-750eb99e0ec12f9a13446284d493d35a60866624.tar.xz | |
drm/i915: fix DP AUX register definitions on Haswell
The old rule that the AUX registers are just an offset (+4 and +10)
from output_reg is not true anymore, since output_reg in on the CPU
and some AUX regs are on the PCH.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: use the existing #defines as spotted by Damien Lespiau.]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 57dbb49..07208bc 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -356,6 +356,29 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, uint32_t aux_clock_divider; int try, precharge; + if (IS_HASWELL(dev)) { + switch (intel_dp->port) { + case PORT_A: + ch_ctl = DPA_AUX_CH_CTL; + ch_data = DPA_AUX_CH_DATA1; + break; + case PORT_B: + ch_ctl = PCH_DPB_AUX_CH_CTL; + ch_data = PCH_DPB_AUX_CH_DATA1; + break; + case PORT_C: + ch_ctl = PCH_DPC_AUX_CH_CTL; + ch_data = PCH_DPC_AUX_CH_DATA1; + break; + case PORT_D: + ch_ctl = PCH_DPD_AUX_CH_CTL; + ch_data = PCH_DPD_AUX_CH_DATA1; + break; + default: + BUG(); + } + } + intel_dp_check_edp(intel_dp); /* The clock divider is based off the hrawclk, * and would like to run at 2MHz. So, take the |