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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-27 13:50:28 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-11 22:50:57 (GMT) |
| commit | fff367c752f5fb998882c7bc0a213ab1e53857db (patch) | |
| tree | 8e1be4691dfd4e0659bdb9f1dd020894cd5b8239 /drivers | |
| parent | cd986abbac6044c76b95fd512bc62329ef9959d0 (diff) | |
| download | linux-fsl-qoriq-fff367c752f5fb998882c7bc0a213ab1e53857db.tar.xz | |
drm/i915: clarify why we need to enable fdi plls so early
For reference, see "Graphics BSpec: vol4g North Display Engine
Registers [IVB], Display Mode Set Sequence", step 4 of the enabling
sequence:
a. "Enable PCH FDI Receiver PLL, wait for warmup plus DMI latency
b. "Switch from Rawclk to PCDclk in FDI Receiver
c. "Enable CPU FDI Transmitter PLL, wait for warmup"
Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 54b1794..612b410 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3227,6 +3227,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) is_pch_port = ironlake_crtc_driving_pch(crtc); if (is_pch_port) { + /* Note: FDI PLL enabling _must_ be done before we enable the + * cpu pipes, hence this is separate from all the other fdi/pch + * enabling. */ ironlake_fdi_pll_enable(intel_crtc); } else { assert_fdi_tx_disabled(dev_priv, pipe); |