diff options
author | Michael Hennerich <michael.hennerich@analog.com> | 2007-10-21 08:54:27 (GMT) |
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committer | Bryan Wu <bryan.wu@analog.com> | 2007-10-21 08:54:27 (GMT) |
commit | 590031450a52c373bf72f5fb156fbcc0c78c6f2c (patch) | |
tree | 0e631bc6e8af9422635535459aaaf10fdddab357 /include/asm-blackfin/mach-bf527/defBF52x_base.h | |
parent | cfa76f024f7c9e65169425804e5b32e71f66d0ee (diff) | |
download | linux-fsl-qoriq-590031450a52c373bf72f5fb156fbcc0c78c6f2c.tar.xz |
Blackfin arch: add new processor ADSP-BF52x arch/mach support
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf527/defBF52x_base.h')
-rw-r--r-- | include/asm-blackfin/mach-bf527/defBF52x_base.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h index b1ff67d..d6c24c54 100644 --- a/include/asm-blackfin/mach-bf527/defBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h @@ -52,13 +52,13 @@ #define SYSCR 0xFFC00104 /* System Configuration Register */ #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ -#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ +#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ -#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ -#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ +#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ +#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ /* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */ #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ @@ -691,6 +691,8 @@ /* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ + +#if 0 #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ @@ -732,6 +734,7 @@ #define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */ #define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */ #define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */ +#endif /* SIC_IAR0 Macros */ #define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */ |