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| author | Luke Browning <lukebr@linux.vnet.ibm.com> | 2008-04-27 18:41:55 (GMT) |
|---|---|---|
| committer | Jeremy Kerr <jk@ozlabs.org> | 2008-05-05 03:33:44 (GMT) |
| commit | f3d69e0507f84903059d456c5d19f10b2df3ac69 (patch) | |
| tree | f8aa4062bc1a0939d7bdb3a634c01869f2bb32a2 /include/asm-powerpc | |
| parent | 7a2142002f29a7b398c49da9bdec712dc57087c7 (diff) | |
| download | linux-fsl-qoriq-f3d69e0507f84903059d456c5d19f10b2df3ac69.tar.xz | |
[POWERPC] spufs: fix concurrent delivery of class 0 & 1 exceptions
SPU class 0 & 1 exceptions may occur in parallel, so we may end up
overwriting csa.dsisr.
This change adds dedicated fields for each class to the spu and the spu
context so that fault data is not overwritten.
Signed-off-by: Luke Browning <lukebr@linux.vnet.ibm.com>
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/spu.h | 8 | ||||
| -rw-r--r-- | include/asm-powerpc/spu_csa.h | 3 |
2 files changed, 7 insertions, 4 deletions
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h index e3c845b..882aa95 100644 --- a/include/asm-powerpc/spu.h +++ b/include/asm-powerpc/spu.h @@ -128,9 +128,11 @@ struct spu { unsigned int irqs[3]; u32 node; u64 flags; - u64 dar; - u64 dsisr; u64 class_0_pending; + u64 class_0_dar; + u64 class_0_dsisr; + u64 class_1_dar; + u64 class_1_dsisr; size_t ls_size; unsigned int slb_replace; struct mm_struct *mm; @@ -143,7 +145,7 @@ struct spu { void (* wbox_callback)(struct spu *spu); void (* ibox_callback)(struct spu *spu); - void (* stop_callback)(struct spu *spu); + void (* stop_callback)(struct spu *spu, int irq); void (* mfc_callback)(struct spu *spu); char irq_c0[8]; diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h index 0ab6bff..129ec14 100644 --- a/include/asm-powerpc/spu_csa.h +++ b/include/asm-powerpc/spu_csa.h @@ -254,7 +254,8 @@ struct spu_state { u64 spu_chnldata_RW[32]; u32 spu_mailbox_data[4]; u32 pu_mailbox_data[1]; - u64 dar, dsisr, class_0_pending; + u64 class_0_dar, class_0_dsisr, class_0_pending; + u64 class_1_dar, class_1_dsisr; unsigned long suspend_time; spinlock_t register_lock; }; |