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authorRoland Dreier <rolandd@cisco.com>2005-11-07 08:58:12 (GMT)
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-07 15:53:26 (GMT)
commit41aace4fe81e3da52fa80b8380e5d2d084f77691 (patch)
treed98b965682efa0e940d9564eafdd8eb69e616ffe /include/asm-ppc/ibm44x.h
parentfcc188e7fdddd8b23f900e485e6b3db05e7375f4 (diff)
downloadlinux-fsl-qoriq-41aace4fe81e3da52fa80b8380e5d2d084f77691.tar.xz
[PATCH] ppc32: Dump error status for both PLB segments on 440SP
The PowerPC 440SP SoC has two Processor Local Bus (PLB) segments (a high-throughput segment and a low-latency segment). Fix our PLB register definitions to cope with this, and add code to dump the status of both segments when a machine check occurs. Signed-off-by: Roland Dreier <rolandd@cisco.com> Cc: Matt Porter <mporter@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc/ibm44x.h')
-rw-r--r--include/asm-ppc/ibm44x.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 197a9ff..0c2ba03 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -302,6 +302,23 @@
#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
+#if defined(CONFIG_440SP)
+/* 440SP PLB Arbiter DCRs */
+#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
+#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
+
+#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */
+#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */
+#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */
+#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */
+#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */
+
+#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */
+#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */
+#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */
+#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */
+#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */
+#else
/* 440GP/GX PLB Arbiter DCRs */
#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
@@ -309,6 +326,7 @@
#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
+#endif
/* 440GP/GX PLB to OPB bridge DCRs */
#define DCRN_POB0_BESR0 0x090